Cypress CY7C1473BV33, CY7C1475BV33, CY7C1471BV33 manual Switching Waveforms, Bw Ad, Address, Stall

Page 26

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Switching Waveforms (continued)

Figure 6 shows NOP, STALL and DESELECT Cycles waveform.[20, 21, 23]

Figure 6. NOP, STALL, and DESELECT Cycles

1 2 3 4

CLK

CEN

ADV/LD

WE
BW [A:D]
ADDRESS	A1	A2		A3
DQ		D(A1)		Q(A2)
COMMAND	WRITE	READ	STALL	READ
	WRITE	READ	STALL	READ
	D(A1)	Q(A2)		Q(A3)

A4			A5
				tCHZ
Q(A3)		D(A4)		Q(A5)
				tDOH
WRITE	STALL	NOP	READ	DESELECT	CONTINUE
D(A4)			Q(A5)		DESELECT

DON’T CARE

UNDEFINED

Note

23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

Document #: 001-15029 Rev. *B

Page 26 of 32

[+] Feedback

Image 26

Contents Description 133 MHz 117 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Functional Overview Single Read AccessesBurst Read Accesses Linear Burst Address Table ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table Used Truth TableAddress Operation Function Truth Table for Read/WriteRead/write truth table for CY7C1471BV33 follows.1, 2 Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set OverviewTAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram Circuitry5V TAP AC Test Conditions TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M x Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientParameter Description Test Conditions Tqfp Fbga Unit Max CapacitanceThermal Resistance 5V IO Test LoadMin Max Switching CharacteristicsParameter Description 133 MHz 117 MHz Unit Min Rite ReadAddress Switching WaveformsBW AD StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/KKVTMP Issue Orig. of Change Description of Change DateDocument History VKN/AESA