CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document History Page
Document Title: CY7C1471BV33/CY7C1473BV33/CY7C1475BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-15029
| REV. | ECN NO. | Issue | Orig. of Change | Description of Change |
| Date |
| | | | |
| | | | | |
| ** | 1024500 | See ECN | VKN/KKVTMP | New Data Sheet |
| | | | | |
| *A | 1274731 | See ECN | VKN/AESA | Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform |
| | | | | |
| *B | 2183566 | See ECN | VKN/PYRS | Converted from preliminary to final |
| | | | | Added footnote 16 related to IDD |
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Document #: 001-15029 Rev. *B | Revised March 05, 2008 | Page 32 of 32 |
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.