Cypress CY7C1473BV33 Document History, Issue Orig. of Change Description of Change Date, Vkn/Aesa

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CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document History Page

Document Title: CY7C1471BV33/CY7C1473BV33/CY7C1475BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Document Number: 001-15029

REV.

ECN NO.

Issue

Orig. of Change

Description of Change

Date

 

 

 

 

 

 

 

 

 

**

1024500

See ECN

VKN/KKVTMP

New Data Sheet

 

 

 

 

 

*A

1274731

See ECN

VKN/AESA

Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform

 

 

 

 

 

*B

2183566

See ECN

VKN/PYRS

Converted from preliminary to final

 

 

 

 

Added footnote 16 related to IDD

© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-15029 Rev. *B

Revised March 05, 2008

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NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Features Selection Guide Functional DescriptionDescription 133 MHz 117 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Functional Overview Single Read AccessesBurst Read Accesses Linear Burst Address Table ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table Used Truth TableAddress Operation Function Truth Table for Read/WriteRead/write truth table for CY7C1471BV33 follows.1, 2 Disabling the Jtag Feature Test Access Port TAPPerforming a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set OverviewTAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram CircuitryTAP DC Electrical Characteristics and Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M x Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceParameter Description Test Conditions Tqfp Fbga Unit Max 5V IO Test LoadMin Max Switching CharacteristicsParameter Description 133 MHz 117 MHz Unit Min Rite ReadSwitching Waveforms BW ADAddress StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN/KKVTMP VKN/AESA