Cypress CY7C1471BV33, CY7C1473BV33 Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M ×, NC/1G

Page 7

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Pin Configuration (continued)

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1475BV33 (1M × 72)

1

2

3

4

5

6

7

8

9

10

11

A

DQg

A

CE2

A

3

A

DQb

ADV/LD

CE

B

DQg

c

g

NC

A

b

f

DQb

BWS

WE

BWS

C

DQg

h

d

NC/576M

1

NC

e

a

DQb

BWS

CE

BWS

D

DQg

VSS

NC/1G

NC

VSS

NC

OE

DQb

E

DQPg

DQPc

VDDQ

VDD

VDDQ

DQPf

DQPb

F

DQc

VSS

NC

VSS

DQf

G

DQc

VDDQ

VDD

NC

VDD

VDDQ

DQf

H

DQc

VSS

NC

VSS

DQf

J

DQc

VDDQ

VDD

NC

VDD

VDDQ

DQf

K

NC

CLK

NC

VSS

CEN

NC

L

DQh

VDDQ

VDD

NC

VDD

VDDQ

DQa

M

DQh

VSS

NC

VSS

DQa

N

DQh

VDDQ

VDD

NC

VDD

VDDQ

DQa

P

DQh

VSS

ZZ

VSS

DQa

R

DQPd

DQPh

VDDQ

VDD

VDDQ

DQPa

DQPe

T

DQd

VSS

NC

MODE

NC

VSS

DQe

U

DQd

NC/144M

A

NC/288M

DQe

V

DQd

A

A1

A

DQe

W

DQd

TMS

TDI

A

A0

A

TDO

TCK

DQe

Document #: 001-15029 Rev. *B

Page 7 of 32

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 117 MHz UnitLogic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1471BV33 2M xLogic Block Diagram CY7C1475BV33 1M x CY7C1471BV33 Pin ConfigurationCY7C1473BV33 CY7C1473BV33 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M ×Pin Definitions Burst Read Accesses Single Read AccessesFunctional Overview Interleaved Burst Address Table ZZ Mode Electrical CharacteristicsLinear Burst Address Table Address Operation Truth TableUsed Read/write truth table for CY7C1471BV33 follows.1, 2 Truth Table for Read/WriteFunction Ieee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetOverview TAP Instruction SetTEST-LOGIC Reset RUN-TEST Idle TAP Controller State DiagramCircuitry TAP Controller Block DiagramGND VIN Vddq TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsTAP Timing TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range5V IO Test Load CapacitanceThermal Resistance Parameter Description Test Conditions Tqfp Fbga Unit MaxParameter Description 133 MHz 117 MHz Unit Min Switching CharacteristicsMin Max Read RiteStall Switching WaveformsBW AD AddressZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA Issue Orig. of Change Description of Change DateDocument History VKN/KKVTMP