Cypress CY7C1473BV33, CY7C1475BV33, CY7C1471BV33 manual Truth Table, Address Operation, Used

Page 11

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.[1, 2, 3, 4, 5, 6, 7]

Truth Table

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

CE1

CE2

CE3

ZZ

ADV/LD

 

WE

 

 

BWX

 

OE

 

 

CEN

CLK

DQ

Used

 

 

 

 

 

 

Deselect Cycle

None

H

X

 

X

 

L

L

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle

None

X

X

 

H

 

L

L

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle

None

X

L

 

X

 

L

L

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Continue Deselect Cycle

None

X

X

 

X

 

L

H

 

X

 

 

X

 

X

 

 

L

L->H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

External

L

H

 

L

 

L

L

 

H

 

 

X

 

L

 

 

L

L->H

Data Out (Q)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

Next

X

X

 

X

 

L

H

 

X

 

 

X

 

L

 

 

L

L->H

Data Out (Q)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Dummy Read

External

L

H

 

L

 

L

L

 

H

 

 

X

 

H

 

 

L

L->H

Tri-State

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read

Next

X

X

 

X

 

L

H

 

X

 

 

X

 

H

 

 

L

L->H

Tri-State

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle

External

L

H

 

L

 

L

L

 

L

 

 

L

 

X

 

 

L

L->H

Data In (D)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle

Next

X

X

 

X

 

L

H

 

X

 

 

L

 

X

 

 

L

L->H

Data In (D)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Write Abort

None

L

H

 

L

 

L

L

 

L

 

 

H

 

X

 

 

L

L->H

Tri-State

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Abort

Next

X

X

 

X

 

L

H

 

X

 

 

H

 

X

 

 

L

L->H

Tri-State

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ignore Clock Edge (Stall)

Current

X

X

 

X

 

L

X

 

X

 

 

X

 

X

 

 

H

L->H

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode

None

X

X

 

X

 

H

X

 

X

 

 

X

 

X

 

 

X

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

1.X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects are asserted, see section Truth Table for Read/Write on page 12 for details.

2.Write is defined by BWX, and WE. See section Truth Table for Read/Write on page 12.

3.When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.

4.The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5.CEN = H, inserts wait states.

6.Device powers up deselected with the IOs in a tri-state condition, regardless of OE.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.

Document #: 001-15029 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 117 MHz UnitLogic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1471BV33 2M xLogic Block Diagram CY7C1475BV33 1M x CY7C1471BV33 Pin ConfigurationCY7C1473BV33 CY7C1473BV33 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M ×Pin Definitions Functional Overview Single Read AccessesBurst Read Accesses Linear Burst Address Table ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table Used Truth TableAddress Operation Function Truth Table for Read/WriteRead/write truth table for CY7C1471BV33 follows.1, 2 Ieee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetOverview TAP Instruction SetTEST-LOGIC Reset RUN-TEST Idle TAP Controller State DiagramCircuitry TAP Controller Block DiagramGND VIN Vddq TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsTAP Timing TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M x Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range5V IO Test Load CapacitanceThermal Resistance Parameter Description Test Conditions Tqfp Fbga Unit MaxMin Max Switching CharacteristicsParameter Description 133 MHz 117 MHz Unit Min Read RiteStall Switching WaveformsBW AD AddressZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA Issue Orig. of Change Description of Change DateDocument History VKN/KKVTMP
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