Cypress CY7C1473BV33 Boundary Scan Exit Order 2M x, Boundary Scan Exit Order 4M x, Bit # Ball ID

Page 20

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33

Boundary Scan Exit Order (2M x 36)

Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	C1		21	R3		41	J11

2	D1		22	P2		42	K10

3	E1		23	R4		43	J10

4	D2		24	P6		44	H11

5	E2		25	R6		45	G11

6	F1		26	R8		46	F11

7	G1		27	P3		47	E11

8	F2		28	P4		48	D10

9	G2		29	P8		49	D11

10	J1		30	P9		50	C11

11	K1		31	P10		51	G10

12	L1		32	R9		52	F10

13	J2		33	R10		53	E10

14	M1		34	R11		54	A9

15	N1		35	N11		55	B9

16	K2		36	M11		56	A10

17	L2		37	L11		57	B10

18	M2		38	M10		58	A8

19	R1		39	L10		59	B8

20	R2		40	K11		60	A7

Bit #

165-Ball ID

61B7

62B6

63A6

64B5

65A5

66A4

67B4

68B3

69A3

70A2

71B2

Boundary Scan Exit Order (4M x 18)

Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	D2		14	R4		27	L10		40	B10

2	E2		15	P6		28	K10		41	A8

3	F2		16	R6		29	J10		42	B8

4	G2		17	R8		30	H11		43	A7

5	J1		18	P3		31	G11		44	B7

6	K1		19	P4		32	F11		45	B6

7	L1		20	P8		33	E11		46	A6

8	M1		21	P9		34	D11		47	B5

9	N1		22	P10		35	C11		48	A4

10	R1		23	R9		36	A11		49	B3

11	R2		24	R10		37	A9		50	A3

12	R3		25	R11		38	B9		51	A2

13	P2		26	M10		39	A10		52	B2

Document #: 001-15029 Rev. *B

Page 20 of 32

[+] Feedback

Image 20

Contents Features Selection Guide Functional DescriptionDescription 133 MHz 117 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Functional Overview Single Read AccessesBurst Read Accesses Linear Burst Address Table ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table Used Truth TableAddress Operation Function Truth Table for Read/WriteRead/write truth table for CY7C1471BV33 follows.1, 2 Disabling the Jtag Feature Test Access Port TAPPerforming a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set OverviewTAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram CircuitryTAP DC Electrical Characteristics and Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M x Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceParameter Description Test Conditions Tqfp Fbga Unit Max 5V IO Test LoadMin Max Switching CharacteristicsParameter Description 133 MHz 117 MHz Unit Min Rite ReadSwitching Waveforms BW ADAddress StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN/KKVTMP VKN/AESA