Cypress CY7C1471BV33, CY7C1475BV33, CY7C1473BV33 manual Pin Configuration

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CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Pin Configuration

Figure 1. 100-Pin TQFP Pinout

BYTE C

BYTE D

DQPC

DQC

DQC

VDDQ

VSS

DQC DQC DQC DQC

VSS VDDQ

DQC DQC

NC

VDD

NC

VSS

DQD

DQD

VDDQ

VSS

DQD DQD DQD DQD

VSS VDDQ

DQD DQD

DQPD

A			A			CE		CE		BW		BW		BW		BW		CE		V			V			CLK			WE		CEN		OE			ADV/LD		A			A		A			A
A			A			CE		CE		BW		BW		BW		BW		CE		V			V			CLK			WE		CEN		OE			ADV/LD		A			A		A			A
						1		2		D		C		B		A	3				DD			SS
																					DD			SS



100			99			98		97		96		95		94		93	92			91			90			89			88		87		86		85			84			83		82			81
1																																														80
2																																														79
3																																														78
4																																														77
5																																														76
6																																														75
7																																														74
8																																														73
9																																														72
10																																														71
11																																														70
12																																														69
13																	CY7C1471BV33																													68
14																	CY7C1471BV33																													67
14																																														67
15																																														66
16																																														65
17																																														64
18																																														63
19																																														62
20																																														61
21																																														60
22																																														59
23																																														58
24																																														57
25																																														56
26																																														55
27																																														54
28																																														53
29																																														52
30																																														51
31			32			33		34		35		36		37		38	39			40			41			42			43		44		45		46			47			48		49			50


	MODE			A		A		A		A		A1		A0		NC/288M		NC/144M			V			V			A		A		A		A				A		A			A	A				A
																					SS			DD

DQPB

DQB DQB

VDDQ

VSS

DQB DQB DQB DQB

VSS

VDDQ

DQB DQB

VSS

NC

VDD

ZZ

DQA DQA

VDDQ

VSS

DQA DQA DQA DQA

VSS

VDDQ

DQA DQA DQPA

BYTE B

BYTE A

Document #: 001-15029 Rev. *B

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Contents Features Selection Guide Functional DescriptionDescription 133 MHz 117 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Burst Read Accesses Single Read AccessesFunctional Overview Interleaved Burst Address Table ZZ Mode Electrical CharacteristicsLinear Burst Address Table Address Operation Truth TableUsed Read/write truth table for CY7C1471BV33 follows.1, 2 Truth Table for Read/WriteFunction Disabling the Jtag Feature Test Access Port TAPPerforming a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set OverviewTAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram CircuitryTAP DC Electrical Characteristics and Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceParameter Description Test Conditions Tqfp Fbga Unit Max 5V IO Test LoadParameter Description 133 MHz 117 MHz Unit Min Switching CharacteristicsMin Max Rite ReadSwitching Waveforms BW ADAddress StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN/KKVTMP VKN/AESA