CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Identification Register Definitions
Instruction Field | CY7C1471BV33 | CY7C1473BV33 | CY7C1475BV33 | Description | |
(2Mx36) | (4Mx18) | (1Mx72) | |||
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Revision Number (31:29) | 000 | 000 | 000 | Describes the version number | |
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Device Depth (28:24)[12] | 01011 | 01011 | 01011 | Reserved for internal use | |
Architecture/Memory Type(23:18) | 001001 | 001001 | 001001 | Defines memory type and architecture | |
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Bus Width/Density(17:12) | 100100 | 010100 | 110100 | Defines width and density | |
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Cypress JEDEC ID Code (11:1) | 00000110100 | 00000110100 | 00000110100 | Enables unique identification of SRAM | |
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| vendor | |
ID Register Presence Indicator (0) | 1 | 1 | 1 | Indicates the presence of an ID | |
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Scan Register Sizes
Register Name | Bit Size (x36) | Bit Size (x18) | Bit Size (x72) |
Instruction | 3 | 3 | 3 |
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Bypass | 1 | 1 | 1 |
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ID | 32 | 32 | 32 |
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Boundary Scan Order – 165FBGA | 71 | 52 | - |
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Boundary Scan Order – 209BGA | - | - | 110 |
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Identification Codes
Instruction | Code | Description |
EXTEST | 000 | Captures IO ring contents. Places the boundary scan register between TDI |
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| and TDO. Forces all SRAM outputs to |
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IDCODE | 001 | Loads the ID register with the vendor ID code and places the register |
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| between TDI and TDO. This operation does not affect SRAM operations. |
SAMPLE Z | 010 | Captures IO ring contents. Places the boundary scan register between TDI |
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| and TDO. Forces all SRAM output drivers to a |
RESERVED | 011 | Do Not Use: This instruction is reserved for future use. |
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SAMPLE/PRELOAD | 100 | Captures IO ring contents. Places the boundary scan register between TDI |
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| and TDO. Does not affect SRAM operation. This instruction does not |
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| implement 1149.1 preload function and is therefore not 1149.1 compliant. |
RESERVED | 101 | Do Not Use: This instruction is reserved for future use. |
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RESERVED | 110 | Do Not Use: This instruction is reserved for future use. |
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BYPASS | 111 | Places the bypass register between TDI and TDO. This operation does not |
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| affect SRAM operations. |
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: | Page 19 of 32 |
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