Cypress CY7C1471BV33, CY7C1475BV33 manual Identification Register Definitions, Scan Register Sizes

Page 19

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Identification Register Definitions

Instruction Field

CY7C1471BV33

CY7C1473BV33

CY7C1475BV33

Description

(2Mx36)

(4Mx18)

(1Mx72)

 

 

Revision Number (31:29)

000

000

000

Describes the version number

 

 

 

 

 

Device Depth (28:24)[12]

01011

01011

01011

Reserved for internal use

Architecture/Memory Type(23:18)

001001

001001

001001

Defines memory type and architecture

 

 

 

 

 

Bus Width/Density(17:12)

100100

010100

110100

Defines width and density

 

 

 

 

 

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

00000110100

Enables unique identification of SRAM

 

 

 

 

vendor

ID Register Presence Indicator (0)

1

1

1

Indicates the presence of an ID

 

 

 

 

register

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x18)

Bit Size (x72)

Instruction

3

3

3

 

 

 

 

Bypass

1

1

1

 

 

 

 

ID

32

32

32

 

 

 

 

Boundary Scan Order – 165FBGA

71

52

-

 

 

 

 

Boundary Scan Order – 209BGA

-

-

110

 

 

 

 

Identification Codes

Instruction

Code

Description

EXTEST

000

Captures IO ring contents. Places the boundary scan register between TDI

 

 

and TDO. Forces all SRAM outputs to High-Z state. This instruction is not

 

 

1149.1-compliant.

IDCODE

001

Loads the ID register with the vendor ID code and places the register

 

 

between TDI and TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures IO ring contents. Places the boundary scan register between TDI

 

 

and TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures IO ring contents. Places the boundary scan register between TDI

 

 

and TDO. Does not affect SRAM operation. This instruction does not

 

 

implement 1149.1 preload function and is therefore not 1149.1 compliant.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not

 

 

affect SRAM operations.

Note

12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 001-15029 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 117 MHz UnitLogic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1471BV33 2M xLogic Block Diagram CY7C1475BV33 1M x CY7C1471BV33 Pin ConfigurationCY7C1473BV33 CY7C1473BV33 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M ×Pin Definitions Burst Read Accesses Single Read AccessesFunctional Overview Interleaved Burst Address Table ZZ Mode Electrical CharacteristicsLinear Burst Address Table Address Operation Truth TableUsed Read/write truth table for CY7C1471BV33 follows.1, 2 Truth Table for Read/WriteFunction Ieee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetOverview TAP Instruction SetTEST-LOGIC Reset RUN-TEST Idle TAP Controller State DiagramCircuitry TAP Controller Block DiagramGND VIN Vddq TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsTAP Timing TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range5V IO Test Load CapacitanceThermal Resistance Parameter Description Test Conditions Tqfp Fbga Unit MaxParameter Description 133 MHz 117 MHz Unit Min Switching CharacteristicsMin Max Read RiteStall Switching WaveformsBW AD AddressZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA Issue Orig. of Change Description of Change DateDocument History VKN/KKVTMP