Cypress CY7C1475BV33, CY7C1471BV33, CY7C1473BV33 manual Truth Table for Read/Write, Function

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CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

The read/write truth table for CY7C1471BV33 follows.[1, 2, 8]

Truth Table for Read/Write

Function

WE

BW

A

BW

B

BW

C

BW

D

Read

H

X

X

X

X

Write No bytes written

L

H

H

H

H

Write Byte A – (DQA and DQPA)

L

L

H

H

H

Write Byte B – (DQB and DQPB)

L

H

L

H

H

Write Byte C – (DQC and DQPC)

L

H

H

L

H

Write Byte D – (DQD and DQPD)

L

H

H

H

L

Write All Bytes

L

L

L

L

L

The read/write truth table for CY7C1473BV33 follows.[1, 2, 8]

Truth Table for Read/Write

Function

WE

BW

a

BW

b

Read

H

X

X

Write – No Bytes Written

L

H

H

Write Byte a – (DQa and DQPa)

L

L

H

Write Byte b – (DQb and DQPb)

L

H

L

Write Both Bytes

L

L

L

The read/write truth table for CY7C1475BV33 follows.[1, 2, 8]

Truth Table for Read/Write

Function		WE			BW		x
Read		H				X

Write – No Bytes Written		L				H

Write Byte X − (DQx and DQPx)		L				L
Write All Bytes		L		All				= L
Write All Bytes		L		All		BW		= L

Note

8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.

Document #: 001-15029 Rev. *B

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Contents Features Selection Guide Functional DescriptionDescription 133 MHz 117 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Single Read Accesses Burst Read AccessesFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address TableLinear Burst Address Table Truth Table Address OperationUsed Truth Table for Read/Write Read/write truth table for CY7C1471BV33 follows.1, 2Function Disabling the Jtag Feature Test Access Port TAPPerforming a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set OverviewTAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram CircuitryTAP DC Electrical Characteristics and Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceParameter Description Test Conditions Tqfp Fbga Unit Max 5V IO Test LoadSwitching Characteristics Parameter Description 133 MHz 117 MHz Unit MinMin Max Rite ReadSwitching Waveforms BW ADAddress StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Orig. of Change Description of Change Date Document HistoryVKN/KKVTMP VKN/AESA