Cypress CY7C1471BV33, CY7C1473BV33 manual Logic Block Diagram CY7C1475BV33 1M x

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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33

Logic Block Diagram – CY7C1475BV33 (1M x 72)

 

 

 

 

 

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

A1

 

 

A1'

 

 

 

 

 

 

 

D1

Q1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0

BURST Q0 A0'

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

O

 

 

 

 

 

 

 

 

 

 

U

 

U

 

 

 

 

 

 

 

 

 

S

T

D

T

 

 

 

 

 

 

 

 

 

P

P

 

ADV/LD

 

 

 

 

 

 

 

E

U

A

U

 

BW a

 

 

 

 

 

 

 

N

T

T

T

 

 

 

 

 

 

 

MEMORY

S

R

A

B

 

BW b

 

 

 

 

 

WRITE

E

S

 

 

 

 

 

 

ARRAY

 

E

U

 

BW c

 

 

WRITE REGISTRY

 

 

DRIVERS

 

A

G

T

F

 

BW d

 

AND DATA COHERENCY

 

 

 

M

I

E

F

 

 

 

 

 

P

S

E

E

 

BW e

 

 

CONTROL LOGIC

 

 

 

 

S

T

R

R

 

BW f

 

 

 

 

 

 

 

 

E

I

S

 

 

 

 

 

 

 

 

 

R

N

 

 

BW g

 

 

 

 

 

 

 

 

S

G

 

 

 

 

 

 

 

 

 

 

E

E

 

BW h

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

 

 

INPUT

E

 

 

 

 

 

 

 

 

REGISTER 1 E

 

 

REGISTER 0

 

OE

READ LOGIC

 

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

Sleep Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph

Document #: 001-15029 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 117 MHz UnitLogic Block Diagram CY7C1473BV33 4M x Logic Block Diagram CY7C1471BV33 2M xLogic Block Diagram CY7C1475BV33 1M x CY7C1471BV33 Pin ConfigurationCY7C1473BV33 CY7C1473BV33 4M x Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M xNC/1G Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M ×Pin Definitions Single Read Accesses Burst Read AccessesFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address TableLinear Burst Address Table Truth Table Address OperationUsed Truth Table for Read/Write Read/write truth table for CY7C1471BV33 follows.1, 2Function Ieee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetOverview TAP Instruction SetTEST-LOGIC Reset RUN-TEST Idle TAP Controller State DiagramCircuitry TAP Controller Block DiagramGND VIN Vddq TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsTAP Timing TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range5V IO Test Load CapacitanceThermal Resistance Parameter Description Test Conditions Tqfp Fbga Unit MaxSwitching Characteristics Parameter Description 133 MHz 117 MHz Unit MinMin Max Read RiteStall Switching WaveformsBW AD AddressZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA Issue Orig. of Change Description of Change DateDocument History VKN/KKVTMP