Cypress CY7C1470V33, CY7C1474V33 Partial Write Cycle Description1, 2, 3, Function CY7C1472V33

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CY7C1470V33

CY7C1472V33

CY7C1474V33

Partial Write Cycle Description[1, 2, 3, 8]

Function (CY7C1470V33)

WE

BWd

BWc

BWb

BWa

Read

H

X

X

X

X

Write – No bytes written

L

H

H

H

H

Write Byte a – (DQa and DQPa)

L

H

H

H

L

Write Byte b – (DQb and DQPb)

L

H

H

L

H

Write Bytes b, a

L

H

H

L

L

Write Byte c – (DQc and DQPc)

L

H

L

H

H

Write Bytes c, a

L

H

L

H

L

Write Bytes c, b

L

H

L

L

H

Write Bytes c, b, a

L

H

L

L

L

Write Byte d – (DQd and DQPd)

L

L

H

H

H

Write Bytes d, a

L

L

H

H

L

Write Bytes d, b

L

L

H

L

H

Write Bytes d, b, a

L

L

H

L

L

Write Bytes d, c

L

L

L

H

H

Write Bytes d, c, a

L

L

L

H

L

Write Bytes d, c, b

L

L

L

L

H

Write All Bytes

L

L

L

L

L

Function (CY7C1472V33)

WE

BW

b

BW

a

Read

H

x

x

Write – No Bytes Written

L

H

H

Write Byte a – (DQa and DQPa)

L

H

L

Write Byte b – (DQb and DQPb)

L

L

H

Write Both Bytes

L

L

L

Function (CY7C1474V33)

WE

BW

x

Read

H

x

Write – No Bytes Written

L

H

Write Byte X − (DQx and DQPx)

L

L

Write All Bytes

L

All

= L

BW

Note:

8.Table only lists a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate Write will be done based on which Byte Write is active.

Document #: 38-05289 Rev. *I

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1470V33 2M x Cypress Semiconductor Corporation250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1472V33 4M xMaximum Access Time Maximum Operating Current Maximum Cmos Standby CurrentPin Configurations Pin Tqfp Packages 4M xCY7C1472V33 4M x BWS Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Address Used Function CY7C1472V33 Partial Write Cycle Description1, 2, 3Function CY7C1470V33 BW d BW c BW b BW a Function CY7C1474V33TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9TAP Timing Output Times3V TAP AC Test Conditions 5V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID J10 Boundary Scan Exit Order 1M xA11 W10Operating Range Electrical Characteristics Over the Operating Range13Maximum Ratings Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Set-up Times CEN Switching WaveformsRead/Write/Timing22, 23 Address A1 A2ZZ Mode Timing26 NOP, Stall and Deselect Cycles22, 23Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistoryRXU VKN