Cypress CY7C1472V33, CY7C1470V33 manual Identification Register Definitions, Scan Register Sizes

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						CY7C1470V33
						CY7C1472V33
						CY7C1474V33
						CY7C1474V33


Identification Register Definitions

Instruction Field			CY7C1470V33	CY7C1472V33	CY7C1474V33	Description
Instruction Field			(2M x 36)	(4M x 18)	(1M x 72)	Description
Revision Number (31:29)			000	000	000	Describes the version number

Device Depth (28:24)[12]			01011	01011	01011	Reserved for internal use
Architecture/Memory			001000	001000	001000	Defines memory type and archi-
Type(23:18)						tecture
Bus Width/Density(17:12)			100100	010100	110100	Defines width and density

Cypress JEDEC ID Code			00000110100	00000110100	00000110100	Allows unique identification of
(11:1)						SRAM vendor
ID Register Presence			1	1	1	Indicates the presence of an ID
Indicator (0)						register

Scan Register Sizes

Register Name	Bit Size (x36)	Bit Size (x18)	Bit Size (x72)
Instruction	3	3	3

Bypass	1	1	1

ID	32	32	32

Boundary Scan Order - 165 FBGA	71	52	-

Boundary Scan Order - 209 FBGA	-	-	110

Identification Codes

Instruction	Code	Description
EXTEST	000	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI
		and TDO. This operation does not affect SRAM operations.
SAMPLE Z	010	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Does not affect SRAM operation. This instruction does not implement 1149.1 preload
		function and is therefore not 1149.1 compliant.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

Note:

12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05289 Rev. *I

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1470V33 2M x Functional DescriptionMaximum Cmos Standby Current Logic Block Diagram-CY7C1472V33 4M xMaximum Access Time Maximum Operating Current 250 MHz 200 MHz 167 MHz Unit4M x Pin Configurations Pin Tqfp PackagesCY7C1472V33 4M x BWS Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Address Used Function CY7C1474V33 Partial Write Cycle Description1, 2, 3Function CY7C1470V33 BW d BW c BW b BW a Function CY7C1472V33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit Clock5V TAP AC Test Conditions 3V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID W10 Boundary Scan Exit Order 1M xA11 J10Ambient Range Electrical Characteristics Over the Operating Range13Maximum Ratings Operating RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 16 250 200 167 Parameter Description Unit Min MaxSet-up Times Address A1 A2 Switching WaveformsRead/Write/Timing22, 23 CENNOP, Stall and Deselect Cycles22, 23 ZZ Mode Timing26Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN RXU