Cypress CY7C1470V33 Boundary Scan Exit Order 2M x, Boundary Scan Exit Order 4M x, Bit # Ball ID

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CY7C1470V33

CY7C1472V33

CY7C1474V33

Boundary Scan Exit Order (2M x 36)

Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	C1		21	R3		41	J11

2	D1		22	P2		42	K10

3	E1		23	R4		43	J10

4	D2		24	P6		44	H11

5	E2		25	R6		45	G11

6	F1		26	R8		46	F11

7	G1		27	P3		47	E11

8	F2		28	P4		48	D10

9	G2		29	P8		49	D11

10	J1		30	P9		50	C11

11	K1		31	P10		51	G10

12	L1		32	R9		52	F10

13	J2		33	R10		53	E10

14	M1		34	R11		54	A9

15	N1		35	N11		55	B9

16	K2		36	M11		56	A10

17	L2		37	L11		57	B10

18	M2		38	M10		58	A8

19	R1		39	L10		59	B8

20	R2		40	K11		60	A7

Boundary Scan Exit Order (4M x 18)

Bit #	165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	D2		14	R4		27	L10

2	E2		15	P6		28	K10

3	F2		16	R6		29	J10

4	G2		17	R8		30	H11

5	J1		18	P3		31	G11

6	K1		19	P4		32	F11

7	L1		20	P8		33	E11

8	M1		21	P9		34	D11

9	N1		22	P10		35	C11

10	R1		23	R9		36	A11

11	R2		24	R10		37	A9

12	R3		25	R11		38	B9

13	P2		26	M10		39	A10

Bit #

165-Ball ID

61B7

62B6

63A6

64B5

65A5

66A4

67B4

68B3

69A3

70A2

71B2

Bit #	165-Ball ID
40	B10

41	A8

42	B8

43	A7

44	B7

45	B6

46	A6

47	B5

48	A4

49	B3

50	A3

51	A2

52	B2

Document #: 38-05289 Rev. *I

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Contents Features Logic Block Diagram-CY7C1470V33 2M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1472V33 4M x Maximum Access Time Maximum Operating Current250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby CurrentPin Configurations Pin Tqfp Packages 4M xCY7C1472V33 4M x BWS Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Address Used Partial Write Cycle Description1, 2, 3 Function CY7C1470V33 BW d BW c BW b BW aFunction CY7C1472V33 Function CY7C1474V33TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetTAP AC Switching Characteristics Over the Operating Range9 TAP TimingParameter Description Min Max Unit Clock Output Times3V TAP AC Test Conditions 5V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x A11J10 W10Electrical Characteristics Over the Operating Range13 Maximum RatingsOperating Range Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Set-up Times Switching Waveforms Read/Write/Timing22, 23CEN Address A1 A2ZZ Mode Timing26 NOP, Stall and Deselect Cycles22, 23Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistoryRXU VKN