Cypress CY7C1474V33, CY7C1472V33, CY7C1470V33 manual Bws

Page 5

CY7C1470V33

CY7C1472V33

CY7C1474V33

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474V33 (1M x 72)

1

2

3

4

5

6

7

8

9

10

11

A

DQg

DQg

A

CE2

A

A

3

A

DQb

DQb

ADV/LD

CE

B

DQg

DQg

c

g

NC

A

b

f

DQb

DQb

BWS

BWS

WE

BWS

BWS

C

DQg

DQg

h

d

NC/576M

1

NC

e

a

DQb

DQb

BWS

BWS

CE

BWS

BWS

D

DQg

DQg

VSS

NC/1G

NC

NC

VSS

NC

OE

DQb

DQb

E

DQPg

DQPc

VDDQ

VDDQ

VDD

VDD

VDD

VDDQ

VDDQ

DQPf

DQPb

F

DQc

DQc

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQf

DQf

G

DQc

DQc

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQf

DQf

H

DQc

DQc

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQf

DQf

J

DQc

DQc

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQf

DQf

K

NC

NC

CLK

NC

VSS

VSS

CEN

NC

NC

NC

NC

L

DQh

DQh

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQa

DQa

M

DQh

DQh

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQa

DQa

N

DQh

DQh

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQa

DQa

P

DQh

DQh

VSS

VSS

VSS

ZZ

VSS

VSS

VSS

DQa

DQa

R

DQPd

DQPh

VDDQ

VDDQ

VDD

VDD

VDD

VDDQ

VDDQ

DQPa

DQPe

T

DQd

DQd

VSS

NC

NC

MODE

NC

NC

VSS

DQe

DQe

U

DQd

DQd

NC/144M

A

A

A

A

A

NC/288M

DQe

DQe

V

DQd

DQd

A

A

A

A1

A

A

A

DQe

DQe

W

DQd

DQd

TMS

TDI

A

A0

A

TDO

TCK

DQe

DQe

Document #: 38-05289 Rev. *I

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Contents Logic Block Diagram-CY7C1470V33 2M x FeaturesFunctional Description Cypress Semiconductor CorporationMaximum Access Time Maximum Operating Current Logic Block Diagram-CY7C1472V33 4M x250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby Current4M x Pin Configurations Pin Tqfp PackagesCY7C1472V33 4M x BWS Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Operation Address Used Function CY7C1470V33 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1472V33 Function CY7C1474V33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterTAP Timing TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output Times5V TAP AC Test Conditions 3V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Bit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x A11 Boundary Scan Exit Order 1M xJ10 W10Maximum Ratings Electrical Characteristics Over the Operating Range13Operating Range Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance Set-up Times Switching Characteristics Over the Operating Range 16250 200 167 Parameter Description Unit Min Max Read/Write/Timing22, 23 Switching WaveformsCEN Address A1 A2NOP, Stall and Deselect Cycles22, 23 ZZ Mode Timing26Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN RXU