Cypress CY7C1470V33, CY7C1474V33 manual CY7C1472V33 4M x

Page 4

CY7C1470V33

CY7C1472V33

CY7C1474V33

Pin Configurations (continued)

165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470V33 (2M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

A

1

c

b

3

A

A

NC

CE

BW

BW

CE

CEN

ADV/LD

B

NC/1G

A

CE2

d

a

CLK

A

A

NC

BW

BW

WE

OE

C

DQPc

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPb

D

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

E

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

F

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

G

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

K

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

L

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

M

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

N

DQPd

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

DQPa

P

NC/144M

A

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

A

A

A

TMS

A0

TCK

A

A

A

A

CY7C1472V33 (4M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/576M

A

NC

A

A

A

CE

1

BW

b

CE

3

CEN

ADV/LD

B

NC/1G

A

CE2

NC

CLK

A

A

NC

BW

a

WE

OE

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DQPa

D

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

E

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

F

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

G

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

H

NC

NC

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

K

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

L

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

M

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

N

DQPb

NC

VDDQ

VSS

NC

NC

NC

VSS

VDDQ

NC

NC

P

NC/144M

A

A

A

TDI

A1

TDO

A

A

A

NC/288M

R

MODE

A

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05289 Rev. *I

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Contents Features Logic Block Diagram-CY7C1470V33 2M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1472V33 4M x Maximum Access Time Maximum Operating Current250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby CurrentPin Configurations Pin Tqfp Packages 4M xCY7C1472V33 4M x BWS Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Address Used Partial Write Cycle Description1, 2, 3 Function CY7C1470V33 BW d BW c BW b BW aFunction CY7C1472V33 Function CY7C1474V33TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetTAP AC Switching Characteristics Over the Operating Range9 TAP TimingParameter Description Min Max Unit Clock Output Times3V TAP AC Test Conditions 5V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID Boundary Scan Exit Order 1M x A11J10 W10Electrical Characteristics Over the Operating Range13 Maximum RatingsOperating Range Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Set-up Times Switching Waveforms Read/Write/Timing22, 23CEN Address A1 A2ZZ Mode Timing26 NOP, Stall and Deselect Cycles22, 23Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistoryRXU VKN