CY7C1470V33
CY7C1472V33
CY7C1474V33
Switching Characteristics Over the Operating Range [16, 17]
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| Description |
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| Unit |
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| Min. | Max. | Min. | Max. | Min. | Max. | |||
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tPower[18] |
| VCC (typical) to the First Access Read or Write | 1 |
| 1 |
| 1 |
| ms | |||||||
Clock |
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tCYC |
| Clock Cycle Time | 4.0 |
| 5.0 |
| 6.0 |
| ns | |||||||
FMAX |
| Maximum Operating Frequency |
| 250 |
| 200 |
| 167 | MHz | |||||||
tCH |
| Clock HIGH | 2.0 |
| 2.0 |
| 2.2 |
| ns | |||||||
tCL |
| Clock LOW | 2.0 |
| 2.0 |
| 2.2 |
| ns | |||||||
Output Times |
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tCO |
| Data Output Valid After CLK Rise |
| 3.0 |
| 3.0 |
| 3.4 | ns | |||||||
tOEV |
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| LOW to Output Valid |
| 3.0 |
| 3.0 |
| 3.4 | ns | |||||
OE |
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tDOH |
| Data Output Hold After CLK Rise | 1.3 |
| 1.3 |
| 1.5 |
| ns | |||||||
tCHZ |
| Clock to |
| 3.0 |
| 3.0 |
| 3.4 | ns | |||||||
tCLZ |
| Clock to | 1.3 |
| 1.3 |
| 1.5 |
| ns | |||||||
tEOHZ |
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| HIGH to Output |
| 3.0 |
| 3.0 |
| 3.4 | ns | |||||
OE |
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tEOLZ |
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| LOW to Output | 0 |
| 0 |
| 0 |
| ns | |||||
OE |
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tAS |
| Address | 1.4 |
| 1.4 |
| 1.5 |
| ns | |||||||
tDS |
| Data Input | 1.4 |
| 1.4 |
| 1.5 |
| ns | |||||||
tCENS |
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| 1.4 |
| 1.4 |
| 1.5 |
| ns | |||
CEN |
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tWES |
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| x | 1.4 |
| 1.4 |
| 1.5 |
| ns | |
WE, | BW |
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tALS |
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ADV/LD | 1.4 |
| 1.4 |
| 1.5 |
| ns | |||||||||
tCES |
| Chip Select | 1.4 |
| 1.4 |
| 1.5 |
| ns | |||||||
Hold Times |
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tAH |
| Address Hold After CLK Rise | 0.4 |
| 0.4 |
| 0.5 |
| ns | |||||||
tDH |
| Data Input Hold After CLK Rise | 0.4 |
| 0.4 |
| 0.5 |
| ns | |||||||
tCENH |
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| Hold After CLK Rise | 0.4 |
| 0.4 |
| 0.5 |
| ns | ||||
CEN |
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tWEH |
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| x Hold After CLK Rise | 0.4 |
| 0.4 |
| 0.5 |
| ns | |
WE, | BW |
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tALH |
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ADV/LD | Hold after CLK Rise | 0.4 |
| 0.4 |
| 0.5 |
| ns | ||||||||
tCEH |
| Chip Select Hold After CLK Rise | 0.4 |
| 0.4 |
| 0.5 |
| ns |
Notes:
16.Timing reference is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18.This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.
19.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from
20.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
21.This parameter is sampled and not 100% tested.
Document #: | Page 20 of 29 |
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