Cypress CY7C1474V33, CY7C1470V33 Logic Block Diagram-CY7C1472V33 4M x, MHz 200 MHz 167 MHz Unit

CY7C1470V33

CY7C1472V33

CY7C1474V33

Logic Block Diagram-CY7C1472V33 (4M x 18)

	A0, A1, A	ADDRESS
		REGISTER 0	A1 D1	Q1 A1'
	MODE		A0 D0 BURST Q0 A0'
			ADV/LD	LOGIC
CLK	C
			C
CEN
		WRITE ADDRESS	WRITE ADDRESS
		REGISTER 1	REGISTER 2

O

O

U

U

S

T

D

T

P

P

ADV/LD

E

U

A

U

WRITE REGISTRY

N

T

T

T

MEMORY

S

R

A

B

BWa

AND DATA COHERENCY

WRITE

E

DQs

ARRAY

E

S

U

CONTROL LOGIC

DRIVERS

A

G

DQPa

T

F

BWb

M

I

E

F

DQPb

P

S

E

E

T

S

R

R

E

I

S

WE

R

N

S

G

E

E

INPUT

E

INPUT

E

REGISTER 1

REGISTER 0

OE

READ LOGIC

CE1

CE2

CE3

ZZ

Sleep

Control

Logic Block Diagram-CY7C1474V33 (1M x 72)

A0, A1, A

ADDRESS

REGISTER 0

A1 D1

Q1 A1'

MODE

A0 D0 BURST Q0 A0'

LOGIC

CLK

C

ADV/LD

C

CEN

WRITE ADDRESS

WRITE ADDRESS

REGISTER 1

REGISTER 2

O

O

U

U

T

T

ADV/LD

S

P

D

P

E

U

A

U

BWa

WRITE REGISTRY

N

T

T

T

MEMORY

S

R

A

BWb

AND DATA COHERENCY

WRITE

E

S

B

DQs

CONTROL LOGIC

ARRAY

A

E

U

BWc

DRIVERS

G

T

F

DQPa

BWd

M

I

E

F

DQPb

P

S

E

E

BWe

S

T

R

R

DQPc

E

S

BWf

R

I

DQPd

N

BWg

S

G

DQPe

E

E

BWh

DQPf

DQPg

DQPh

WE

INPUT

E

INPUT

E

REGISTER 1

REGISTER 0

OE

READ LOGIC

CE1

CE2

CE3

ZZ

Sleep

Control

Selection Guide

	250 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	3.0	3.0	3.4	ns
Maximum Operating Current	500	500	450	mA
Maximum CMOS Standby Current	120	120	120	mA

Document #: 38-05289 Rev. *I Page 2 of 29

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