Cypress CY7C1474V33, CY7C1472V33, CY7C1470V33 manual Rxu, Vkn

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CY7C1470V33

CY7C1472V33

CY7C1474V33

Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05289

REV.	ECN No.	Issue Date	Orig. of	Description of Change
REV.	ECN No.	Issue Date	Change	Description of Change

*H	416221	See ECN	RXU	Converted from Preliminary to Final
				Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Changed Three-state to Tri-state
				Changed the description of IX from Input Load Current to Input Leakage
				Current on page# 18
				Changed the IX current values of MODE on page # 18 from –5 ∝A and 30 ∝A
				to –30 ∝A and 5 ∝A
				Changed the IX current values of ZZ on page # 18 from –30 ∝A and 5 ∝A
				to –5 ∝A and 30 ∝A
				Changed VDDQ < VDD to VDDQ < VDD in page #18
				Replaced Package Name column with Package Diagram in the Ordering
				Information table
				Updated the Ordering Information Table
*I	472335	See ECN	VKN	Corrected the typo in the pin configuration for 209-Ball FBGA pinout
				(Corrected the ball name for H9 to VSS from VSSQ).
				Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
				Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
				AC Switching Characteristics table.
				Updated the Ordering Information table.

Document #: 38-05289 Rev. *I

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Contents Logic Block Diagram-CY7C1470V33 2M x FeaturesFunctional Description Cypress Semiconductor CorporationMaximum Access Time Maximum Operating Current Logic Block Diagram-CY7C1472V33 4M x250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby Current4M x Pin Configurations Pin Tqfp PackagesCY7C1472V33 4M x BWS Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Operation Address Used Function CY7C1470V33 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1472V33 Function CY7C1474V33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterTAP Timing TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output Times5V TAP AC Test Conditions 3V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Bit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x A11 Boundary Scan Exit Order 1M xJ10 W10Maximum Ratings Electrical Characteristics Over the Operating Range13Operating Range Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance Set-up Times Switching Characteristics Over the Operating Range 16250 200 167 Parameter Description Unit Min Max Read/Write/Timing22, 23 Switching WaveformsCEN Address A1 A2NOP, Stall and Deselect Cycles22, 23 ZZ Mode Timing26Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN RXU