Cypress CY7C1472V33 Switching Waveforms, Read/Write/Timing22, 23, Cen, Address A1 A2, DON’T Care

Page 21

CY7C1470V33

CY7C1472V33

CY7C1474V33

Switching Waveforms

Read/Write/Timing[22, 23, 24]

1

2 t CYC 3

CLK

 

tCENS tCENH

tCH tCL

CEN

tCES tCEH

CE

ADV/LD

WE

BWx

ADDRESS A1 A2

 

4

 

5

6

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

A4

A5

 

tCO

 

8 9

A6 A7

10

tAS tAH

tDS tDH

tCLZ

tDOH

tOEV tCHZ

Data

D(A1)

In-Out (DQ)

OE

D(A2) D(A2+1) Q(A3) Q(A4)

tOEHZ

Q(A4+1) D(A5)

tDOH tOELZ

Q(A6)

WRITE

WRITE

BURST

D(A1)

D(A2)

WRITE

 

 

D(A2+1)

READ

READ

BURST

WRITE

READ

WRITE

Q(A3)

Q(A4)

READ

D(A5)

Q(A6)

D(A7)

 

 

Q(A4+1)

 

 

 

DESELECT

DON’T CARE

UNDEFINED

Notes:

22.For this waveform ZZ is tied LOW.

23.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

24.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.

Document #: 38-05289 Rev. *I

Page 21 of 29

[+] Feedback

Image 21
Contents Logic Block Diagram-CY7C1470V33 2M x FeaturesFunctional Description Cypress Semiconductor CorporationMaximum Access Time Maximum Operating Current Logic Block Diagram-CY7C1472V33 4M x250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby Current4M x Pin Configurations Pin Tqfp PackagesCY7C1472V33 4M x BWS Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Address Used Function CY7C1470V33 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1472V33 Function CY7C1474V33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterTAP Timing TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output Times5V TAP AC Test Conditions 3V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID A11 Boundary Scan Exit Order 1M xJ10 W10Maximum Ratings Electrical Characteristics Over the Operating Range13Operating Range Ambient RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 16 250 200 167 Parameter Description Unit Min MaxSet-up Times Read/Write/Timing22, 23 Switching WaveformsCEN Address A1 A2NOP, Stall and Deselect Cycles22, 23 ZZ Mode Timing26Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN RXU