Cypress CY7C1472V33, CY7C1470V33, CY7C1474V33 manual Ball Fbga 14 x 22 x 1.76 mm

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CY7C1470V33

CY7C1472V33

CY7C1474V33

Package Diagrams (continued)

209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)

51-85167-**

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05289 Rev. *I

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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1470V33 2M x Functional DescriptionMaximum Cmos Standby Current Logic Block Diagram-CY7C1472V33 4M xMaximum Access Time Maximum Operating Current 250 MHz 200 MHz 167 MHz Unit4M x Pin Configurations Pin Tqfp PackagesCY7C1472V33 4M x BWS Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Address Used Function CY7C1474V33 Partial Write Cycle Description1, 2, 3Function CY7C1470V33 BW d BW c BW b BW a Function CY7C1472V33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit Clock5V TAP AC Test Conditions 3V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID W10 Boundary Scan Exit Order 1M xA11 J10Ambient Range Electrical Characteristics Over the Operating Range13Maximum Ratings Operating RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 16 250 200 167 Parameter Description Unit Min MaxSet-up Times Address A1 A2 Switching WaveformsRead/Write/Timing22, 23 CENNOP, Stall and Deselect Cycles22, 23 ZZ Mode Timing26Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN RXU