Cypress CY7C1474V33, CY7C1472V33, CY7C1470V33 3V TAP AC Test Conditions, 5V TAP AC Test Conditions

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CY7C1470V33

CY7C1472V33

CY7C1474V33

3.3V TAP AC Test Conditions

Input pulse levels	VSS to 3.3V
Input rise and fall times	1 ns
Input timing reference levels	1.5V
Output reference levels	1.5V
Test load termination supply voltage	1.5V

2.5V TAP AC Test Conditions

Input pulse levels	VSS to 2.5V
Input rise and fall time	1 ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

1.5V

1.25V

50Ω

50Ω

TDO

TDO

ZO= 50Ω

20pF

ZO= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]

Parameter	Description	Test Conditions		Min.	Max.	Unit
VOH1	Output HIGH Voltage	IOH = –4.0 mA,VDDQ = 3.3V		2.4		V
		IOH = –1.0 mA,VDDQ = 2.5V		2.0		V
VOH2	Output HIGH Voltage	IOH = –100 µA	VDDQ = 3.3V	2.9		V
			VDDQ = 2.5V	2.1		V
VOL1	Output LOW Voltage	IOL = 8.0 mA	VDDQ = 3.3V		0.4	V
		IOL = 1.0 mA	VDDQ = 2.5V		0.4	V
VOL2	Output LOW Voltage	IOL = 100 µA	VDDQ = 3.3V		0.2	V
			VDDQ = 2.5V		0.2	V
VIH	Input HIGH Voltage		VDDQ = 3.3V	2.0	VDD + 0.3	V
			VDDQ = 2.5V	1.7	VDD + 0.3	V
VIL	Input LOW Voltage		VDDQ = 3.3V	–0.3	0.8	V
			VDDQ = 2.5V	–0.3	0.7	V
IX	Input Load Current	GND < VIN < VDDQ		–5	5	µA

Note:

11. All voltages referenced to VSS (GND).

Document #: 38-05289 Rev. *I

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1470V33 2M x Cypress Semiconductor Corporation250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1472V33 4M xMaximum Access Time Maximum Operating Current Maximum Cmos Standby CurrentPin Configurations Pin Tqfp Packages 4M xCY7C1472V33 4M x BWS Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsPin Name Type Pin Description Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Operation Address Used Function CY7C1472V33 Partial Write Cycle Description1, 2, 3Function CY7C1470V33 BW d BW c BW b BW a Function CY7C1474V33TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9TAP Timing Output Times3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Bit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x J10 Boundary Scan Exit Order 1M xA11 W10Operating Range Electrical Characteristics Over the Operating Range13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance Set-up Times Switching Characteristics Over the Operating Range 16250 200 167 Parameter Description Unit Min Max CEN Switching WaveformsRead/Write/Timing22, 23 Address A1 A2ZZ Mode Timing26 NOP, Stall and Deselect Cycles22, 23Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistoryRXU VKN