Cypress CY7C1470V33 manual TAP Timing, TAP AC Switching Characteristics Over the Operating Range9

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CY7C1470V33

CY7C1472V33

CY7C1474V33

possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

Test Data-Out

 

(TDO)

 

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics Over the Operating Range[9, 10]

Parameter

Description

Min.

Max

Unit

Clock

 

 

 

 

 

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH time

20

 

ns

tTL

TCK Clock LOW time

20

 

ns

Output Times

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Set-up Times

 

 

 

 

tTMSS

TMS Set-up to TCK Clock Rise

5

 

ns

tTDIS

TDI Set-up to TCK Clock Rise

5

 

ns

tCS

Capture Set-up to TCK Rise

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes:

9.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 38-05289 Rev. *I

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Contents Logic Block Diagram-CY7C1470V33 2M x FeaturesFunctional Description Cypress Semiconductor CorporationMaximum Access Time Maximum Operating Current Logic Block Diagram-CY7C1472V33 4M x250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby Current4M x Pin Configurations Pin Tqfp PackagesCY7C1472V33 4M x BWS Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Address Used Function CY7C1470V33 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1472V33 Function CY7C1474V33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterTAP Timing TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output Times5V TAP AC Test Conditions 3V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID A11 Boundary Scan Exit Order 1M xJ10 W10Maximum Ratings Electrical Characteristics Over the Operating Range13Operating Range Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Set-up Times Read/Write/Timing22, 23 Switching WaveformsCEN Address A1 A2NOP, Stall and Deselect Cycles22, 23 ZZ Mode Timing26Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN RXU