Cypress CY7C1472V33, CY7C1470V33, CY7C1474V33 manual 250

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CY7C1470V33

CY7C1472V33

CY7C1474V33

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Part and Package Type		Operating
(MHz)	Ordering Code	Diagram	Part and Package Type		Range

250	CY7C1470V33-250AXC	51-85050	100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free		Commercial

	CY7C1472V33-250AXC

	CY7C1470V33-250BZC	51-85165	165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

	CY7C1472V33-250BZC

	CY7C1470V33-250BZXC	51-85165	165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

	CY7C1472V33-250BZXC

	CY7C1474V33-250BGC	51-85167	209-ball Fine-Pitch Ball Grid Array (14	× 22 × 1.76 mm)

	CY7C1474V33-250BGXC		209-ball Fine-Pitch Ball Grid Array (14	× 22 × 1.76 mm) Lead-Free

	CY7C1470V33-250AXI	51-85050	100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free		Industrial

	CY7C1472V33-250AXI

	CY7C1470V33-250BZI	51-85165	165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

	CY7C1472V33-250BZI

	CY7C1470V33-250BZXI	51-85165	165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

	CY7C1472V33-250BZXI

	CY7C1474V33-250BGI	51-85167	209-ball Fine-Pitch Ball Grid Array (14	× 22 × 1.76 mm)

	CY7C1474V33-250BGXI		209-ball Fine-Pitch Ball Grid Array (14	× 22 × 1.76 mm) Lead-Free

Document #: 38-05289 Rev. *I

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Contents Features Logic Block Diagram-CY7C1470V33 2M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1472V33 4M x Maximum Access Time Maximum Operating Current250 MHz 200 MHz 167 MHz Unit Maximum Cmos Standby CurrentPin Configurations Pin Tqfp Packages 4M xCY7C1472V33 4M x BWS Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Address Used Partial Write Cycle Description1, 2, 3 Function CY7C1470V33 BW d BW c BW b BW aFunction CY7C1472V33 Function CY7C1474V33TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetTAP AC Switching Characteristics Over the Operating Range9 TAP TimingParameter Description Min Max Unit Clock Output Times3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x A11J10 W10Electrical Characteristics Over the Operating Range13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 16 250 200 167 Parameter Description Unit Min MaxSet-up Times Switching Waveforms Read/Write/Timing22, 23CEN Address A1 A2ZZ Mode Timing26 NOP, Stall and Deselect Cycles22, 23Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document HistoryRXU VKN