Cypress CY7C2561KV18, CY7C2563KV18 Maximum Ratings, Operating Range, Electrical Characteristics

Page 21

 

 

PRELIMINARY

CY7C2561KV18, CY7C2576KV18

 

 

CY7C2563KV18, CY7C2565KV18

 

 

 

 

 

 

 

 

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [15]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch-up Current

...................................................

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [19]

VDDQ [19]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [16]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 20

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 21

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

 

–0.15

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

2

 

2

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

2

 

2

μA

VREF

Input Reference Voltage [22]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [23]

VDD Operating Supply

VDD = Max,

550 MHz

(x8)

 

 

900

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

900

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

920

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1310

 

 

 

 

 

 

 

 

 

 

 

 

 

500 MHz

(x8)

 

 

830

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

830

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

850

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1210

 

 

 

 

 

 

 

 

 

 

 

 

 

450 MHz

(x8)

 

 

760

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

760

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

780

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1100

 

 

 

 

 

 

 

 

 

 

 

 

 

400 MHz

(x8)

 

 

690

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

690

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

710

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1000

 

 

 

 

 

 

 

 

 

 

Notes

19.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

20.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

21.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

22.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

23.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-15887 Rev. *E

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Contents Features Configurations Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C2561KV18 Logic Block Diagram CY7C2576KV18Doff Logic Block Diagram CY7C2565KV18 Logic Block Diagram CY7C2563KV18Pin Configuration CY7C2561KV18 8M xCY7C2576KV18 8M x CY7C2563KV18 4M x WPS BWSCY7C2565KV18 2M x Pin Definitions Pin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldProgrammable Impedance Echo ClocksApplication Example Truth TableOperation Comments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceDevice Write cycle description table for CY7C2565KV18 followsInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Controller TAP Electrical CharacteristicsParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Description Scan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump ID Power Up Sequence Power Up Sequence in QDR-II+ SramPLL Constraints VDD / VddqDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitIncluding JIG Scope AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsHigh LOWRead/Write/Deselect Sequence 32, 33 Switching WaveformsOrdering Information 450 Ball Fbga 13 x 15 x 1.4 mm Package DiagramSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History