Cypress CY7C2563KV18, CY7C2565KV18 manual Pin Configuration, CY7C2561KV18 8M x, CY7C2576KV18 8M x

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PRELIMINARY

 

 

 

CY7C2561KV18, CY7C2576KV18

 

 

 

 

 

 

 

 

 

 

 

 

CY7C2563KV18, CY7C2565KV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow.[2]

 

 

 

 

 

 

 

 

 

 

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C2561KV18 (8M x 8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

2

 

3

 

4

 

 

5

 

 

6

 

7

 

 

8

 

9

10

11

A

 

 

 

 

 

A

 

A

 

 

 

 

 

 

 

1

 

 

 

 

NC/144M

 

 

 

A

A

CQ

 

CQ

 

WPS

NWS

K

RPS

B

 

 

NC

NC

 

NC

 

 

A

 

NC/288M

 

K

 

 

 

0

 

A

NC

NC

Q3

 

 

 

 

NWS

 

C

 

 

NC

NC

 

NC

 

 

VSS

 

 

A

 

NC

 

A

 

VSS

NC

NC

D3

D

 

 

NC

D4

 

NC

 

 

VSS

 

 

VSS

 

VSS

 

VSS

 

VSS

NC

NC

NC

E

 

 

NC

NC

 

Q4

 

VDDQ

 

 

VSS

 

VSS

 

VSS

VDDQ

NC

D2

Q2

F

 

 

NC

NC

 

NC

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

NC

NC

G

 

 

NC

D5

 

Q5

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

NC

NC

H

 

 

 

 

 

VREF

 

VDDQ

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

 

 

 

 

J

 

 

NC

NC

 

NC

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

Q1

D1

K

 

 

NC

NC

 

NC

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

NC

NC

L

 

 

NC

Q6

 

D6

 

VDDQ

 

 

VSS

 

VSS

 

VSS

VDDQ

NC

NC

Q0

M

 

 

NC

NC

 

NC

 

 

VSS

 

 

VSS

 

VSS

 

VSS

 

VSS

NC

NC

D0

N

 

 

NC

D7

 

NC

 

 

VSS

 

 

A

 

 

A

 

A

 

VSS

NC

NC

NC

P

 

 

NC

NC

 

Q7

 

 

A

 

 

A

 

QVLD

 

A

 

A

NC

NC

NC

R

 

TDO

TCK

 

A

 

 

A

 

 

A

 

ODT

 

A

 

A

A

TMS

TDI

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C2576KV18 (8M x 9)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

2

 

3

 

4

 

 

5

 

 

6

 

7

 

 

8

 

9

10

11

A

 

 

 

 

A

 

A

 

 

 

 

 

 

NC

 

 

 

 

NC/144M

 

 

 

A

A

CQ

 

CQ

 

 

 

WPS

 

 

 

K

 

RPS

B

 

 

NC

NC

 

NC

 

 

A

 

NC/288M

 

 

K

 

 

0

 

A

NC

NC

Q4

 

 

 

 

 

 

BWS

 

C

 

 

NC

NC

 

NC

 

 

VSS

 

 

A

 

NC

 

A

 

VSS

NC

NC

D4

D

 

 

NC

D5

 

NC

 

 

VSS

 

 

VSS

 

VSS

 

VSS

 

VSS

NC

NC

NC

E

 

 

NC

NC

 

Q5

 

VDDQ

 

 

VSS

 

VSS

 

VSS

VDDQ

NC

D3

Q3

F

 

 

NC

NC

 

NC

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

NC

NC

G

 

 

NC

D6

 

Q6

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

NC

NC

H

 

 

 

 

 

VREF

 

VDDQ

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

 

 

 

 

J

 

 

NC

NC

 

NC

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

Q2

D2

K

 

 

NC

NC

 

NC

 

VDDQ

 

 

VDD

 

VSS

 

VDD

VDDQ

NC

NC

NC

L

 

 

NC

Q7

 

D7

 

VDDQ

 

 

VSS

 

VSS

 

VSS

VDDQ

NC

NC

Q1

M

 

 

NC

NC

 

NC

 

 

VSS

 

 

VSS

 

VSS

 

VSS

 

VSS

NC

NC

D1

N

 

 

NC

D8

 

NC

 

 

VSS

 

 

A

 

 

A

 

A

 

VSS

NC

NC

NC

P

 

 

NC

NC

 

Q8

 

 

A

 

 

A

 

QVLD

 

A

 

A

NC

D0

Q0

R

 

TDO

TCK

 

A

 

 

A

 

 

A

 

ODT

 

A

 

A

A

TMS

TDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-15887 Rev. *E

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Contents Functional Description Features ConfigurationsCypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C2576KV18 Logic Block Diagram CY7C2561KV18Doff Logic Block Diagram CY7C2563KV18 Logic Block Diagram CY7C2565KV18CY7C2561KV18 8M x Pin ConfigurationCY7C2576KV18 8M x WPS BWS CY7C2563KV18 4M xCY7C2565KV18 2M x Pin Definitions Pin Name Pin Description Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo ClocksTruth Table Application ExampleOperation Write Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C2565KV18 follows DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Electrical Characteristics TAP ControllerParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Register Name Bit Size Instruction Codes DescriptionBoundary Scan Order Bit # Bump ID Power Up Sequence in QDR-II+ Sram Power Up SequencePLL Constraints VDD / VddqElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms Including JIG ScopeSwitching Characteristics Parameter Min MaxHigh LOWSwitching Waveforms Read/Write/Deselect Sequence 32, 33Ordering Information 450 Package Diagram Ball Fbga 13 x 15 x 1.4 mmWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History
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