Cypress CY7C2565KV18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

		PRELIMINARY	CY7C2561KV18, CY7C2576KV18
			CY7C2563KV18, CY7C2565KV18
Table 2. Pin Definitions (continued)
Pin Name	IO		Pin Description

KInput Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.

KInput Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0].

CQ	Echo Clock	Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
		(K) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.
	Echo Clock	Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
CQ
		(K) of the QDR-II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.
ZQ	Input	Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
		impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
		between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
		minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
	Input	PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
DOFF
		in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
		can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I
		mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167
		MHz with QDR-I timing.
TDO	Output	TDO for JTAG.
TCK	Input	TCK Pin for JTAG.
TDI	Input	TDI Pin for JTAG.
TMS	Input	TMS Pin for JTAG.
NC	N/A	Not Connected to the Die. Can be tied to any voltage level.
NC/144M	N/A	Not Connected to the Die. Can be tied to any voltage level.
NC/288M	N/A	Not Connected to the Die. Can be tied to any voltage level.
VREF	Input-	Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
	Reference	measurement points.
VDD	Power Supply	Power Supply Inputs to the Core of the Device.
VSS	Ground	Ground for the Device.
VDDQ	Power Supply	Power Supply Inputs for the Outputs of the Device.

Document Number: 001-15887 Rev. *E Page 7 of 29

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