Cypress CY7C2563KV18, CY7C2561KV18 manual Switching Characteristics, Parameter Min Max, High, Low

PRELIMINARY

CY7C2561KV18, CY7C2576KV18

CY7C2563KV18, CY7C2565KV18

Switching Characteristics

Over the Operating Range [24, 25]

Cypress

Consortium

Description

550 MHz

500 MHz

450 MHz

400 MHz

Unit

Parameter

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

t

POWER

V (Typical) to the First Access [26]

1

1

1

1

ms

DD

tCYC

tKHKH

K Clock Cycle Time

1.81

8.4

2.0

8.4

2.2

8.4

2.5

8.4

ns

tKH

tKHKL

HIGH

0.4

–

0.4

–

0.4

–

0.4

–

ns

Input Clock (K/K)

tKL

tKLKH

LOW

0.4

–

0.4

–

0.4

–

0.4

–

ns

Input Clock (K/K)

tKHKH

tKHKH

K Clock Rise to

Clock Rise

0.77

–

0.85

–

0.94

–

1.06

–

ns

K

(rising edge to rising edge)

Setup Times

tSA

tAVKH

Address Setup to K Clock Rise

0.23

–

0.25

–

0.275

–

0.4

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

0.23

–

0.25

–

0.275

–

0.4

–

ns

(RPS,

WPS)

tSCDDR

tIVKH

Double Data Rate Control Setup to Clock (K/K)

0.18

–

0.20

–

0.22

–

0.28

–

ns

Rise (BWS0, BWS1, BWS2, BWS3)

tSD

tDVKH

0.18

–

0.20

–

0.22

–

0.28

–

ns

D[X:0] Setup to Clock (K/K)

Rise

Hold Times

tHA

tKHAX

Address Hold after K Clock Rise

0.23

–

0.25

–

0.275

–

0.4

–

ns

tHC

tKHIX

Control Hold after K Clock Rise

(RPS,

WPS)

0.23

–

0.25

–

0.275

–

0.4

–

ns

tHCDDR

tKHIX

Double Data Rate Control Hold after Clock (K/K)

0.18

–

0.20

–

0.28

–

0.28

–

ns

Rise (BWS0, BWS1, BWS2, BWS3)

tHD

tKHDX

D

Rise

0.18

–

0.20

–

0.28

–

0.28

–

ns

Hold after Clock (K/K)

[X:0]

Output Times

tCO

tCHQV

K/K

Clock Rise to Data Valid

–

0.29

–

0.33

–

0.37

–

0.45

ns

tDOH

tCHQX

Clock Rise

–0.29

–

–0.33

–

–0.37

–

–0.45

–

ns

Data Output Hold after Output K/K

(Active to Active)

tCCQO

tCHCQV

Clock Rise to Echo Clock Valid

–

0.29

–

0.33

–

0.37

–

0.45

ns

K/K

tCQOH

tCHCQX

Clock Rise

–0.29

–

–0.33

–

–0.37

–

–0.45

–

ns

Echo Clock Hold after K/K

tCQD

tCQHQV

Echo Clock High to Data Valid

0.15

0.15

0.15

0.20

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.15

–

–0.15

–

–0.15

–

–0.20

–

ns

tCQH

tCQHCQL

Output Clock (CQ/CQ)

HIGH [27]

0.655

–

0.75

–

0.85

–

1.0

–

ns

tCQHCQH

tCQHCQH

CQ Clock Rise to

CQ

Clock Rise

0.655

–

0.75

–

0.85

–

1.0

–

ns

(rising edge to rising edge) [27]

tCHZ

tCHQZ

Rise to High-Z

–

0.29

–

0.33

–

0.37

–

0.45

ns

Clock (K/K)

(Active to High-Z) [28, 29]

tCLZ

tCHQX1

Rise to Low-Z [28, 29]

–0.29

–

–0.33

–

–0.37

–

–0.45

–

ns

Clock (K/K)

tQVLD

tCQHQVLD

Echo Clock High to QVLD Valid [30]

–0.15

0.15

–0.15

0.15

–0.15

0.15

–0.20

0.20

ns

PLL Timing

tKC Var

tKC Var

Clock Phase Jitter

–

0.15

–

0.15

–

0.15

–

0.20

ns

tKC lock

tKC lock

PLL Lock Time (K)

20

–

20

–

20

–

20

–

μs

tKC Reset

tKC Reset

K Static to PLL Reset [31]

30

30

30

30

ns

Notes

25.When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

26.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be initiated.

27.These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production.

28.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.

29.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

30.tQVLD spec is applicable for both rising and falling edges of QVLD signal.

31.Hold to >VIH or <VIL.

Document Number: 001-15887 Rev. *E Page 24 of 29

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