Cypress CY7C2561KV18 manual TAP AC Switching Characteristics, TAP Timing and Test Conditions

Page 17

 

 

 

PRELIMINARY

CY7C2561KV18, CY7C2576KV18

 

 

 

CY7C2563KV18, CY7C2565KV18

 

 

 

 

 

 

 

 

 

 

 

 

TAP AC Switching Characteristics

 

 

 

 

 

Over the Operating Range [17, 18]

 

 

 

 

 

Parameter

 

 

Description

 

Min

Max

Unit

tTCYC

TCK Clock Cycle Time

 

50

 

ns

tTF

TCK Clock Frequency

 

 

20

MHz

tTH

TCK Clock HIGH

 

20

 

ns

tTL

TCK Clock LOW

 

20

 

ns

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

 

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

 

5

 

ns

tCS

Capture Setup to TCK Rise

 

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

 

5

 

ns

tTDIH

TDI Hold after Clock Rise

 

5

 

ns

tCH

Capture Hold after Clock Rise

 

5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

 

0

 

ns

TAP Timing and Test Conditions

Figure 4 shows the TAP timing and test conditions. [18]

Figure 4. TAP Timing and Test Conditions

 

 

 

0.9V

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

Z0

= 50Ω

 

 

 

CL = 20 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

1.8V

0.9V

0V

(a)GND

Test Clock

TCK

Test Mode Select

TMS

Test Data In

TDI

Test Data Out

TDO

tTH

tTMSS

tTDIS

tTL

tTCYC

tTMSH

tTDIH

tTDOV

 

 

 

 

t

 

 

 

 

 

 

 

 

TDOX

Notes

17.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

18.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document Number: 001-15887 Rev. *E

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Contents Cypress Semiconductor Corporation 198 Champion Court Features ConfigurationsFunctional Description Doff Logic Block Diagram CY7C2561KV18Logic Block Diagram CY7C2576KV18 Logic Block Diagram CY7C2565KV18 Logic Block Diagram CY7C2563KV18CY7C2576KV18 8M x Pin ConfigurationCY7C2561KV18 8M x CY7C2565KV18 2M x CY7C2563KV18 4M xWPS BWS Pin Definitions Pin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldProgrammable Impedance Echo ClocksOperation Application ExampleTruth Table Comments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceDevice Write cycle description table for CY7C2565KV18 followsInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Controller TAP Electrical CharacteristicsParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Description Scan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump ID Power Up Sequence Power Up Sequence in QDR-II+ SramPLL Constraints VDD / VddqDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitIncluding JIG Scope AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsHigh LOWRead/Write/Deselect Sequence 32, 33 Switching WaveformsOrdering Information 450 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions