Cypress CY7C2576KV18 Scan Register Sizes Register Name Bit Size, Instruction Codes Description

Page 18

 

 

 

 

 

 

PRELIMINARY

CY7C2561KV18, CY7C2576KV18

 

 

 

 

 

 

CY7C2563KV18, CY7C2565KV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7. Identification Register Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Field

 

 

 

 

 

 

Value

 

Description

 

CY7C2561KV18

CY7C2576KV18

 

CY7C2563KV18

CY7C2565KV18

 

 

 

 

Revision Number

 

000

 

000

 

000

000

Version number.

(31:29)

 

 

 

 

 

 

 

 

 

 

 

Cypress Device ID

 

11010010001000100

11010010001001100

 

11010010001010100

11010010001100100

Defines the type of

(28:12)

 

 

 

 

 

 

 

 

 

 

SRAM.

Cypress JEDEC ID

 

00000110100

 

00000110100

 

00000110100

00000110100

Allows unique

(11:1)

 

 

 

 

 

 

 

 

 

 

identification of

 

 

 

 

 

 

 

 

 

 

 

SRAM vendor.

ID Register

 

1

 

 

1

 

1

1

Indicates the

Presence (0)

 

 

 

 

 

 

 

 

 

 

presence of an ID

 

 

 

 

 

 

 

 

 

 

 

register.

Table 8. Scan Register Sizes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

 

 

Bit Size

 

Instruction

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

Bypass

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

 

 

32

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan

 

 

 

 

 

 

 

 

109

 

 

 

 

 

 

 

 

 

Table 9. Instruction Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Code

 

 

 

Description

 

EXTEST

 

000

Captures the input and output ring contents.

 

 

 

 

 

 

IDCODE

 

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

 

 

 

 

This operation does not affect SRAM operation.

 

 

SAMPLE Z

 

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

 

RESERVED

 

011

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

SAMPLE/PRELOAD

 

100

Captures the input and output ring contents. Places the boundary scan register between TDI

 

 

 

 

 

 

and TDO. Does not affect the SRAM operation.

 

 

RESERVED

 

101

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

RESERVED

 

110

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

BYPASS

 

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

 

 

 

 

operation.

 

 

 

Document Number: 001-15887 Rev. *E

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Contents Features Configurations Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C2561KV18 Logic Block Diagram CY7C2576KV18Doff Logic Block Diagram CY7C2563KV18 Logic Block Diagram CY7C2565KV18Pin Configuration CY7C2561KV18 8M xCY7C2576KV18 8M x CY7C2563KV18 4M x WPS BWSCY7C2565KV18 2M x Pin Definitions Pin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksApplication Example Truth TableOperation Remains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle description table for CY7C2565KV18 followsDevice Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsParameter Description Test Conditions Min Max Unit TAP Electrical CharacteristicsTAP Controller GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Register Name Bit Size Instruction Codes DescriptionBoundary Scan Order Bit # Bump ID PLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence VDD / VddqMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Operating RangeThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms Including JIG ScopeHigh Switching CharacteristicsParameter Min Max LOWSwitching Waveforms Read/Write/Deselect Sequence 32, 33Ordering Information 450 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History