Cypress CY7C2561KV18, CY7C2576KV18 manual CY7C2563KV18 4M x, Wps Bws, CY7C2565KV18 2M x

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18

 

 

CY7C2563KV18, CY7C2565KV18

 

 

 

 

 

 

 

 

Pin Configuration

The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow.[2] (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C2563KV18 (4M x 18)

 

 

1

 

 

2

3

4

 

 

5

 

6

 

7

 

8

 

9

10

11

A

 

 

 

 

 

NC/144M

A

 

 

 

 

 

1

 

 

 

NC/288M

 

 

 

A

A

CQ

 

CQ

WPS

BWS

K

RPS

B

 

 

NC

Q9

D9

 

A

 

NC

K

 

 

0

 

A

NC

NC

Q8

 

 

BWS

 

C

 

 

NC

NC

D10

 

VSS

 

A

NC

 

A

 

VSS

NC

Q7

D8

D

 

 

NC

D11

Q10

 

VSS

 

VSS

VSS

 

VSS

 

VSS

NC

NC

D7

E

 

 

NC

NC

Q11

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

D6

Q6

F

 

 

NC

Q12

D12

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

Q5

G

 

 

NC

D13

Q13

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

D5

H

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

 

J

 

 

NC

NC

D14

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

Q4

D4

K

 

 

NC

NC

Q14

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

D3

Q3

L

 

 

NC

Q15

D15

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

Q2

M

 

 

NC

NC

D16

 

VSS

 

VSS

VSS

 

VSS

 

VSS

NC

Q1

D2

N

 

 

NC

D17

Q16

 

VSS

 

A

 

A

 

A

 

VSS

NC

NC

D1

P

 

 

NC

NC

Q17

 

A

 

A

QVLD

 

A

 

A

NC

D0

Q0

R

 

TDO

TCK

A

 

A

 

A

ODT

 

A

 

A

A

TMS

TDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C2565KV18 (2M x 36)

 

 

1

 

 

2

3

4

 

5

 

6

 

 

7

 

8

 

9

10

11

A

 

 

 

 

 

NC/288M

A

 

 

 

 

 

2

 

 

 

 

 

1

 

 

 

A

NC/144M

CQ

 

CQ

WPS

BWS

K

BWS

RPS

B

 

Q27

Q18

D18

 

A

 

 

3

 

K

 

 

0

 

A

D17

Q17

Q8

 

BWS

 

BWS

 

C

 

D27

Q28

D19

 

VSS

 

A

NC

 

A

 

VSS

D16

Q7

D8

D

 

D28

D20

Q19

 

VSS

 

VSS

VSS

 

VSS

 

VSS

Q16

D15

D7

E

 

Q29

D29

Q20

VDDQ

 

VSS

VSS

 

VSS

VDDQ

Q15

D6

Q6

F

 

Q30

Q21

D21

VDDQ

 

VDD

VSS

 

VDD

VDDQ

D14

Q14

Q5

G

 

D30

D22

Q22

VDDQ

 

VDD

VSS

 

VDD

VDDQ

Q13

D13

D5

H

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

 

J

 

D31

Q31

D23

VDDQ

 

VDD

VSS

 

VDD

VDDQ

D12

Q4

D4

K

 

Q32

D32

Q23

VDDQ

 

VDD

VSS

 

VDD

VDDQ

Q12

D3

Q3

L

 

Q33

Q24

D24

VDDQ

 

VSS

VSS

 

VSS

VDDQ

D11

Q11

Q2

M

 

D33

Q34

D25

 

VSS

 

VSS

VSS

 

VSS

 

VSS

D10

Q1

D2

N

 

D34

D26

Q25

 

VSS

 

A

 

A

 

A

 

VSS

Q10

D9

D1

P

 

Q35

D35

Q26

 

A

 

A

QVLD

 

A

 

A

Q9

D0

Q0

R

 

TDO

TCK

A

 

A

 

A

ODT

 

A

 

A

A

TMS

TDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-15887 Rev. *E

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Contents Cypress Semiconductor Corporation 198 Champion Court Features ConfigurationsFunctional Description Doff Logic Block Diagram CY7C2561KV18Logic Block Diagram CY7C2576KV18 Logic Block Diagram CY7C2565KV18 Logic Block Diagram CY7C2563KV18CY7C2576KV18 8M x Pin ConfigurationCY7C2561KV18 8M x CY7C2565KV18 2M x CY7C2563KV18 4M xWPS BWS Pin Definitions Pin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldProgrammable Impedance Echo ClocksOperation Application ExampleTruth Table Comments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceDevice Write cycle description table for CY7C2565KV18 followsInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Controller TAP Electrical CharacteristicsParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Description Scan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump ID Power Up Sequence Power Up Sequence in QDR-II+ SramPLL Constraints VDD / VddqDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitIncluding JIG Scope AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsHigh LOWRead/Write/Deselect Sequence 32, 33 Switching WaveformsOrdering Information 450 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions