Cypress CY7C2565KV18, CY7C2563KV18, CY7C2561KV18, CY7C2576KV18 Boundary Scan Order Bit # Bump ID

Page 19

						PRELIMINARY			CY7C2561KV18, CY7C2576KV18
						PRELIMINARY			CY7C2563KV18, CY7C2565KV18
									CY7C2563KV18, CY7C2565KV18

Table 10. Boundary Scan Order

Bit #	Bump ID					Bit #	Bump ID		Bit #	Bump ID		Bit #	Bump ID
0	6R					28	10G		56	6A		84	1J

1	6P					29	9G		57	5B		85	2J

2	6N					30	11F		58	5A		86	3K

3	7P					31	11G		59	4A		87	3J

4	7N					32	9F		60	5C		88	2K

5	7R					33	10F		61	4B		89	1K

6	8R					34	11E		62	3A		90	2L

7	8P					35	10E		63	2A		91	3L

8	9R					36	10D		64	1A		92	1M

9	11P					37	9E		65	2B		93	1L

10	10P					38	10C		66	3B		94	3N

11	10N					39	11D		67	1C		95	3M

12	9P					40	9C		68	1B		96	1N

13	10M					41	9D		69	3D		97	2M

14	11N					42	11B		70	3C		98	3P

15	9M					43	11C		71	1D		99	2N

16	9N					44	9B		72	2C		100	2P

17	11L					45	10B		73	3E		101	1P

18	11M					46	11A		74	2D		102	3R

19	9L					47	10A		75	2E		103	4R

20	10L					48	9A		76	1E		104	4P

21	11K					49	8B		77	2F		105	5P

22	10K					50	7C		78	3F		106	5N

23	9J					51	6C		79	1G		107	5R

24	9K					52	8A		80	1F		108	Internal

25	10J					53	7A		81	3G

26	11J					54	7B		82	2G

27	11H					55	6B		83	1H

Document Number: 001-15887 Rev. *E

Page 19 of 29

[+] Feedback

Image 19

Contents Functional Description Features ConfigurationsCypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C2576KV18 Logic Block Diagram CY7C2561KV18Doff Logic Block Diagram CY7C2565KV18 Logic Block Diagram CY7C2563KV18CY7C2561KV18 8M x Pin ConfigurationCY7C2576KV18 8M x WPS BWS CY7C2563KV18 4M xCY7C2565KV18 2M x Pin Definitions Pin Name Pin Description TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Valid Data Indicator QvldDepth Expansion Programmable ImpedanceTruth Table Application ExampleOperation During the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle description table for CY7C2565KV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramGND ≤ VI ≤ VDD TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Description Scan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump ID VDD / Vddq Power Up Sequence in QDR-II+ SramPower Up Sequence PLL ConstraintsOperating Range Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceIncluding JIG Scope AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence 32, 33 Switching WaveformsOrdering Information 450 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History