Cypress CY7C2576KV18, CY7C2563KV18, CY7C2561KV18, CY7C2565KV18 manual Ordering Information

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18

 

 

CY7C2563KV18, CY7C2565KV18

 

 

 

 

 

 

 

 

Ordering Information

The following table lists all possible speed, package and temperature range options supported for these devices. Note that some options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative for the status of availability of parts.

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID= 201&PageID=230.

Table 11. Ordering Information

Speed

Ordering Code

Package

Package Type

Operating

(MHz)

Diagram

Range

550

CY7C2561KV18-550BZC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Commercial

 

 

 

 

 

 

CY7C2576KV18-550BZC

 

 

 

 

 

 

 

 

 

CY7C2563KV18-550BZC

 

 

 

 

 

 

 

 

 

CY7C2565KV18-550BZC

 

 

 

 

 

 

 

 

 

CY7C2561KV18-550BZXC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C2576KV18-550BZXC

 

 

 

 

 

 

 

 

 

CY7C2563KV18-550BZXC

 

 

 

 

 

 

 

 

 

CY7C2565KV18-550BZXC

 

 

 

 

 

 

 

 

 

CY7C2561KV18-550BZI

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Industrial

 

 

 

 

 

 

CY7C2576KV18-550BZI

 

 

 

 

 

 

 

 

 

CY7C2563KV18-550BZI

 

 

 

 

 

 

 

 

 

CY7C2565KV18-550BZI

 

 

 

 

 

 

 

 

 

CY7C2561KV18-550BZXI

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C2576KV18-550BZXI

 

 

 

 

 

 

 

 

 

CY7C2563KV18-550BZXI

 

 

 

 

 

 

 

 

 

CY7C2565KV18-550BZXI

 

 

 

 

 

 

 

 

500

CY7C2561KV18-500BZC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Commercial

 

 

 

 

 

 

CY7C2576KV18-500BZC

 

 

 

 

 

 

 

 

 

CY7C2563KV18-500BZC

 

 

 

 

 

 

 

 

 

CY7C2565KV18-500BZC

 

 

 

 

 

 

 

 

 

CY7C2561KV18-500BZXC

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C2576KV18-500BZXC

 

 

 

 

 

 

 

 

 

CY7C2563KV18-500BZXC

 

 

 

 

 

 

 

 

 

CY7C2565KV18-500BZXC

 

 

 

 

 

 

 

 

 

CY7C2561KV18-500BZI

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Industrial

 

 

 

 

 

 

CY7C2576KV18-500BZI

 

 

 

 

 

 

 

 

 

CY7C2563KV18-500BZI

 

 

 

 

 

 

 

 

 

CY7C2565KV18-500BZI

 

 

 

 

 

 

 

 

 

CY7C2561KV18-500BZXI

51-85180

165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C2576KV18-500BZXI

 

 

 

 

 

 

 

 

 

CY7C2563KV18-500BZXI

 

 

 

 

 

 

 

 

 

CY7C2565KV18-500BZXI

 

 

 

 

 

 

 

 

Document Number: 001-15887 Rev. *E

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Contents Cypress Semiconductor Corporation 198 Champion Court Features ConfigurationsFunctional Description Doff Logic Block Diagram CY7C2561KV18Logic Block Diagram CY7C2576KV18 Logic Block Diagram CY7C2563KV18 Logic Block Diagram CY7C2565KV18CY7C2576KV18 8M x Pin ConfigurationCY7C2561KV18 8M x CY7C2565KV18 2M x CY7C2563KV18 4M xWPS BWS Pin Definitions Pin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksOperation Application ExampleTruth Table Remains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle description table for CY7C2565KV18 followsDevice Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsParameter Description Test Conditions Min Max Unit TAP Electrical CharacteristicsTAP Controller GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Register Name Bit Size Instruction Codes DescriptionBoundary Scan Order Bit # Bump ID PLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence VDD / VddqMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Operating RangeThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms Including JIG ScopeHigh Switching CharacteristicsParameter Min Max LOWSwitching Waveforms Read/Write/Deselect Sequence 32, 33Ordering Information 450 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions