Cypress CY7C2563KV18, CY7C2561KV18 TAP Electrical Characteristics, TAP Controller, Gnd ≤ Vi ≤ Vdd

Page 16


		PRELIMINARY	CY7C2561KV18, CY7C2576KV18
		PRELIMINARY	CY7C2563KV18, CY7C2565KV18
			CY7C2563KV18, CY7C2565KV18
		Figure 3. TAP Controller Block Diagram
		Figure 3. TAP Controller Block Diagram

TDI

TCK

Selection Circuitry

0

Bypass Register

2 1 0

Instruction Register

31 30 29 . . 2 1 0 Identification Register

108 . . . . 2 1 0

Boundary Scan Register

Selection Circuitry

TDO

TMS

TAP Controller

TAP Electrical Characteristics

Over the Operating Range [14, 15, 16]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35VDD	V
IX	Input and Output Load Current	GND ≤ VI ≤ VDD	–5	5	μA

Notes

14.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

15.Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2).

16.All Voltage referenced to Ground.

Document Number: 001-15887 Rev. *E

Page 16 of 29

[+] Feedback

Image 16

Contents Functional Description Features ConfigurationsCypress Semiconductor Corporation 198 Champion Court Logic Block Diagram CY7C2576KV18 Logic Block Diagram CY7C2561KV18Doff Logic Block Diagram CY7C2563KV18 Logic Block Diagram CY7C2565KV18CY7C2561KV18 8M x Pin ConfigurationCY7C2576KV18 8M x WPS BWS CY7C2563KV18 4M xCY7C2565KV18 2M x Pin Definitions Pin Name Pin Description Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo ClocksTruth Table Application ExampleOperation Write Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C2565KV18 follows DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Electrical Characteristics TAP ControllerParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Register Name Bit Size Instruction Codes DescriptionBoundary Scan Order Bit # Bump ID Power Up Sequence in QDR-II+ Sram Power Up SequencePLL Constraints VDD / VddqElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms Including JIG ScopeSwitching Characteristics Parameter Min MaxHigh LOWSwitching Waveforms Read/Write/Deselect Sequence 32, 33Ordering Information 450 Package Diagram Ball Fbga 13 x 15 x 1.4 mmWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History