Cypress CY7C1464AV33 TAP Controller Block Diagram TAP Controller State Diagram, TAP Registers

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CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

IEEE 1149.1 Serial Boundary Scan (JTAG)

Test Data-In (TDI)

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor- porates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic level.

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most signif- icant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

TAP Controller State Diagram

1

TEST-LOGIC

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

0

RUN-TEST/

1

SELECT

1

SELECT

1

IDLE

 

DR-SCAN

 

IR-SCAN

 

 

 

 

 

 

 

 

0

 

0

 

 

 

 

1

 

1

 

 

 

 

CAPTURE-DR

 

CAPTURE-IR

 

 

 

 

0

 

0

 

 

 

 

SHIFT-DR

0

SHIFT-IR

0

 

 

 

1

 

1

 

 

 

 

 

1

 

1

TDI

Selection Circuitry

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register

 

 

 

 

 

 

 

 

 

 

x

.

.

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Register

Selection Circuitry

TDO

EXIT1-DR

 

EXIT1-IR

 

 

0

 

 

0

 

PAUSE-DR

0

PAUSE-IR

0

 

1

 

 

1

 

0

 

 

0

 

 

EXIT2-DR

 

EXIT2-IR

 

 

1

 

 

1

 

UPDATE-DR

 

UPDATE-IR

 

1

0

 

1

0

 

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

TCK

TMS

 

TAP CONTROLLER

 

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

Document #: 38-05353 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV33 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionPower supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Single Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1460AV33 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1462AV33 2,8Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Scan Register SizesIdentification Codes Instruction Code DescriptionCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball Fbga Boundary Scan OrderBit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Ambient RangeThermal Resistance17 Capacitance17AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

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Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.
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