Cypress CY7C1460AV33, CY7C1462AV33, CY7C1464AV33 Pin Definitions, Pin Name Type Pin Description

Page 5

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV33 (512K x 72)

 

1

2

3

 

4

 

5

6

 

 

 

7

8

 

 

 

9

 

 

10

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

DQg

DQg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

CE2

A

ADV/LD

A

 

 

 

CE3

 

A

DQb

DQb

 

 

 

 

 

 

 

 

 

B

DQg

DQg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

A

 

BWSb

 

 

 

 

DQb

 

 

BWSc

 

BWSg

 

 

WE

 

 

BWSf

DQb

 

 

 

 

 

 

 

C

DQg

DQg

 

 

 

 

 

 

NC/576M

 

 

 

1

 

NC

 

 

 

 

 

 

 

 

 

DQb

 

 

BWS

h

 

BWS

d

 

 

CE

 

 

 

BWS

e

 

BWS

a

DQb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

DQg

DQg

VSS

 

 

NC/1G

 

 

 

 

 

 

 

NC

 

 

 

NC

VSS

 

 

 

NC

 

 

OE

 

 

DQb

DQb

E

DQPg

DQPc

VDDQ

VDDQ

VDD

 

 

VDD

VDD

 

 

VDDQ

 

VDDQ

DQPf

DQPb

F

DQc

DQc

VSS

 

VSS

VSS

 

NC

VSS

 

VSS

 

VSS

DQf

DQf

G

DQc

DQc

VDDQ

 

VDDQ

VDD

 

NC

VDD

 

VDDQ

 

VDDQ

DQf

DQf

H

DQc

DQc

 

VSS

 

VSS

VSS

 

NC

VSS

 

 

VSS

VSS

DQf

DQf

 

 

 

 

 

 

J

DQc

DQc

 

VDDQ

 

VDDQ

VDD

 

NC

VDD

 

 

VDDQ

 

VDDQ

DQf

DQf

K

NC

NC

CLK

 

NC

VSS

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

CEN

 

 

 

NC

 

NC

NC

NC

L

DQh

DQh

VDDQ

 

VDDQ

VDD

 

NC

VDD

 

VDDQ

 

VDDQ

DQa

DQa

M

DQh

DQh

VSS

 

VSS

VSS

 

 

NC

VSS

VSS

 

VSS

DQa

DQa

N

DQh

DQh

VDDQ

 

VDDQ

VDD

 

 

NC

VDD

 

VDDQ

 

VDDQ

DQa

DQa

P

DQh

DQh

VSS

 

VSS

VSS

 

 

ZZ

VSS

 

VSS

 

VSS

DQa

DQa

R

DQPd

DQPh

VDDQ

 

VDDQ

VDD

 

 

VDD

VDD

VDDQ

 

VDDQ

DQPa

DQPe

T

DQd

DQd

VSS

 

NC

NC

 

MODE

NC

 

 

 

NC

 

VSS

DQe

DQe

U

DQd

DQd

NC/144M

 

A

NC/72M

 

 

A

A

 

 

 

A

NC/288M

DQe

DQe

V

DQd

DQd

 

A

 

A

A

 

 

A1

A

 

 

 

A

 

A

DQe

DQe

W

DQd

DQd

TMS

 

TDI

A

 

 

A0

A

 

 

TDO

 

TCK

DQe

DQe

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

Pin Name

I/O Type

 

 

Pin Description

 

 

 

 

 

 

 

 

 

A0

Input-

Address Inputs used to select one of the address locations. Sampled at the rising

 

 

A1

Synchronous

edge of the CLK.

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

a

Input-

Byte Write Select Inputs, active LOW. Qualified with

 

to conduct writes to the SRAM.

 

 

BW

WE

 

 

BWb

Synchronous

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and

 

 

BWc

 

DQPb, BWc controls DQc and DQPc, BW

d controls DQd and DQPd, BWe controls DQe and

 

 

BWd

 

DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and

 

 

BWe

 

DQPh.

 

 

BWf

 

 

 

 

 

 

 

 

 

 

 

BWg

 

 

 

 

 

 

 

 

 

 

 

BWh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if

 

is active

 

 

WE

CEN

 

 

 

 

 

 

 

Synchronous

LOW. This signal must be asserted LOW to initiate a write sequence.

 

 

 

 

 

 

 

Input-

Advance/Load Input used to advance the on-chip address counter or load a new

 

 

ADV/LD

 

 

 

 

 

 

 

 

Synchronous

address. When HIGH (and

CEN

is asserted LOW) the internal burst counter is advanced.

 

 

 

 

 

 

 

 

When LOW, a new address can be loaded into the device for an access. After being

 

 

 

 

 

 

 

 

deselected, ADV/LD should be driven LOW in order to load a new address.

Document #: 38-05353 Rev. *D

 

 

 

 

 

 

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Contents Logic Block Diagram-CY7C1460AV33 1M x FeaturesFunctional Description Cypress Semiconductor Corporation Logic Block Diagram-CY7C1464AV33 512K x Logic Block Diagram-CY7C1462AV33 2M x Selection Guide 250 MHz 200 MHz 167 MHz Unit2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV33 2M × Pin Name Type Pin Description Pin DefinitionsClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Burst Read Accesses Single Read AccessesSingle Write Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Stall Partial Write Cycle Description 1, 2, 3Function CY7C1460AV33 Function CY7C1462AV33 2,8Disabling the Jtag Feature TAP Controller Block Diagram TAP Controller State DiagramTest Access Port TAP Performing a TAP ResetTAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan OrderCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID CY7C14604V33 512K x Bit# Ball ID Ball BGA Boundary Scan Order 13Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Read/Write/Timing24, 25 Switching WaveformsNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of Change
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