Cypress CY7C1462AV33 manual Capacitance17, Thermal Resistance17, AC Test Loads and Waveforms

Page 18

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Capacitance[17]

Parameter

Description

Test Conditions

100 TQFP

165 FBGA

209 FBGA

Unit

Max.

Max.

Max.

 

 

 

 

 

 

 

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

6.5

7

5

pF

 

 

VDD = 2.5V VDDQ = 2.5V

 

 

 

 

CCLK

Clock Input Capacitance

3

7

5

pF

CI/O

Input/Output Capacitance

 

5.5

6

7

pF

Thermal Resistance[17]

Parameters

Description

Test Conditions

100 TQFP

165 FBGA

209 FBGA

Unit

Package

Package

Package

 

 

 

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard

25.21

20.8

25.31

°C/W

 

(Junction to Ambient)

test methods and procedures

 

 

 

 

 

 

for measuring thermal

 

 

 

 

ΘJC

Thermal Resistance

2.28

3.2

4.48

°C/W

impedance, per EIA/JESD51.

 

(Junction to Case)

 

 

 

 

 

AC Test Loads and Waveforms

3.3V I/O Test Load

3.3V

 

 

 

 

R = 317

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z0

= 50

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL

= 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

R = 351

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 1.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

VDDQ

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

90%

10%

 

 

 

 

 

 

90%

 

 

 

 

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

SCOPE

 

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V I/O Test Load

2.5V

 

 

 

 

 

 

 

 

R = 1667

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z0

= 50

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL = 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R =1538

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

 

 

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

17. Tested initially and after any design or process changes that may affect these parameters.

 

 

 

 

 

 

 

 

 

 

(c)

VDDQ

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

90%

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

90%

10%

1 ns

Document #: 38-05353 Rev. *D

Page 18 of 27

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV33 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionPower supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Single Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1460AV33 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1462AV33 2,8Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Scan Register SizesIdentification Codes Instruction Code Description Ball Fbga Boundary Scan Order CY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Bit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Ambient RangeCapacitance17 Thermal Resistance17AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History