Cypress CY7C1464AV33, CY7C1460AV33 manual CY7C1462AV33 2M ×

Page 4

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Pin Configurations (continued)

165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1460AV33 (1M × 36)

 

1

2

3

 

4

 

5

 

 

6

 

7

 

 

 

 

8

 

 

 

 

 

9

10

11

A

NC/576M

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A

NC

 

CE

1

 

BW

c

 

BW

b

 

CE

3

 

CEN

 

 

ADV/LD

 

B

NC/1G

A

CE2

 

 

d

 

 

 

a

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A

NC

 

BW

 

BW

 

WE

OE

C

DQPc

NC

VDDQ

 

VSS

 

 

VSS

 

VSS

 

VSS

VSS

VDDQ

NC

DQPb

D

DQc

DQc

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQb

DQb

E

DQc

DQc

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQb

DQb

F

DQc

DQc

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQb

DQb

G

DQc

DQc

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQb

DQb

H

NC

NC

 

NC

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

NC

NC

ZZ

J

DQd

DQd

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

DQa

K

DQd

DQd

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

DQa

L

DQd

DQd

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

DQa

M

DQd

DQd

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

DQa

N

DQPd

NC

VDDQ

 

VSS

 

 

NC

 

NC

 

 

NC

VSS

VDDQ

NC

DQPa

P

NC/144M

NC/72M

 

A

 

A

 

 

TDI

 

A1

TDO

 

 

A

A

A

NC/288M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

MODE

A

 

A

 

A

 

 

TMS

 

A0

 

TCK

 

 

A

A

A

A

 

 

 

 

 

 

 

CY7C1462AV33 (2M × 18)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

3

 

4

 

5

 

 

6

 

7

 

 

 

 

8

 

 

 

 

 

9

10

11

A

NC/576M

A

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A

A

 

CE

1

 

BW

b

 

 

 

CE

3

 

CEN

 

ADV/LD

 

B

NC/1G

A

CE2

 

NC

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

A

A

NC

 

 

 

BW

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

WE

 

OE

C

NC

NC

VDDQ

 

VSS

 

 

VSS

 

VSS

 

VSS

VSS

VDDQ

NC

DQPa

D

NC

DQb

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

NC

DQa

E

NC

DQb

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

NC

DQa

F

NC

DQb

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

NC

DQa

G

NC

DQb

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

NC

DQa

H

NC

NC

 

NC

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

NC

NC

ZZ

J

DQb

NC

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

NC

K

DQb

NC

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

NC

L

DQb

NC

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

NC

M

DQb

NC

VDDQ

 

VDD

 

 

VSS

 

VSS

 

VSS

VDD

VDDQ

DQa

NC

N

DQPb

NC

VDDQ

 

VSS

 

 

NC

 

NC

 

 

NC

VSS

VDDQ

NC

NC

P

NC/144M

NC/72M

 

A

 

A

 

 

TDI

 

A1

 

TDO

 

 

A

A

A

NC/288M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

MODE

A

 

A

 

A

 

 

TMS

 

A0

 

TCK

 

 

A

A

A

A

Document #: 38-05353 Rev. *D

Page 4 of 27

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Contents Features Logic Block Diagram-CY7C1460AV33 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV33 2M x Logic Block Diagram-CY7C1464AV33 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionPower supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Single Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 StallFunction CY7C1460AV33 Function CY7C1462AV33 2,8TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball Fbga Boundary Scan OrderBit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Ambient RangeThermal Resistance17 Capacitance17AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.