Cypress CY7C1464AV33 manual Features, Functional Description, Cypress Semiconductor Corporation

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CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Features

•Pin-compatible and functionally equivalent to ZBT™

•Supports 250-MHz bus operations with zero wait states

—Available speed grades are 250, 200 and 167 MHz

•Internally self-timed output buffer control to eliminate the need to use asynchronous OE

•Fully registered (inputs and outputs) for pipelined operation

•Byte Write capability

•3.3V power supply

•3.3V/2.5V I/O power supply

•Fast clock-to-output times

—2.6 ns (for 250-MHz device)

•Clock Enable (CEN) pin to suspend operation

•Synchronous self-timed writes

•CY7C1460AV33, CY7C1462AV33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1464AV33 available in lead-free and non-lead-free 209-ball FBGA package

•IEEE 1149.1 JTAG-Compatible Boundary Scan

•Burst capability—linear or interleaved burst order

•“ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The

CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans- ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent

Write/Readtransitions.The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (BWa–BWhfor CY7C1464AV33, BWa–BWdfor CY7C1460AV33 and BWa–BWbfor CY7C1462AV33) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Logic Block Diagram-CY7C1460AV33 (1M x 36)

 

 

 

 

 

 

 

 

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

 

A1

D1

Q1 A1'

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0 BURST Q0 A0'

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

O

 

O

 

 

 

 

 

 

 

 

 

 

 

U

D

 

 

 

 

 

 

 

 

 

 

 

E

T

U

 

 

 

 

 

 

 

 

 

 

 

P

A

T

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

U

T

P

 

 

 

ADV/LD

 

 

 

 

 

 

 

S

T

A

U

 

 

 

 

 

 

 

 

 

 

R

T

 

 

 

 

 

WRITE REGISTRY

 

 

 

MEMORY

E

S

B

 

 

 

BWa

 

AND DATA COHERENCY

 

WRITE

 

 

E

DQs

 

 

 

 

 

ARRAY

 

 

 

BWb

 

CONTROL LOGIC

 

DRIVERS

 

A

G

T

U

DQPa

 

 

 

 

 

 

 

 

I

F

 

 

BWc

 

 

 

 

 

 

 

M

S

E

DQPb

 

 

 

 

 

 

 

 

 

F

 

 

BWd

 

 

 

 

 

 

 

P

T

E

E

DQPc

 

 

 

 

 

 

 

 

 

 

E

 

 

WE

 

 

 

 

 

 

 

S

R

R

R

DQPd

 

 

 

 

 

 

 

 

 

 

 

S

I

S

 

 

 

 

 

 

 

 

 

 

 

 

E

N

E

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

INPUT

E

 

INPUT

E

 

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 0

 

 

 

OE

READ LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

SLEEP

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-05353 Rev. *D

 

 

 

 

 

 

 

 

 

 

Revised June 22, 2006

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Contents Logic Block Diagram-CY7C1460AV33 1M x FeaturesFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1464AV33 512K x Logic Block Diagram-CY7C1462AV33 2M xSelection Guide 250 MHz 200 MHz 167 MHz Unit2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV33 2M × Pin Name Type Pin Description Pin DefinitionsPower supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Burst Read Accesses Single Read AccessesSingle Write Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Stall Partial Write Cycle Description 1, 2, 3Function CY7C1460AV33 Function CY7C1462AV33 2,8Disabling the Jtag Feature TAP Controller Block Diagram TAP Controller State DiagramTest Access Port TAP Performing a TAP ResetTAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball Fbga Boundary Scan OrderBit# Ball ID CY7C14604V33 512K x Bit# Ball ID Ball BGA Boundary Scan Order 13Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Ambient RangeThermal Resistance17 Capacitance17AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Read/Write/Timing24, 25 Switching WaveformsNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of Change

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.
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