CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Features
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•Supports
—Available speed grades are 250, 200 and 167 MHz
•Internally
•Fully registered (inputs and outputs) for pipelined operation
•Byte Write capability
•3.3V power supply
•3.3V/2.5V I/O power supply
•Fast
—2.6 ns (for
•Clock Enable (CEN) pin to suspend operation
•Synchronous
•CY7C1460AV33, CY7C1462AV33 available in
•IEEE 1149.1
•Burst
•“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans- ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent
Write/Readtransitions.The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.
Write operations are controlled by the Byte Write Selects
Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output
Logic Block |
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| A0, A1, A | ADDRESS |
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| REGISTER 0 |
| A1 | D1 | Q1 A1' |
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| MODE |
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| A0 | D0 BURST Q0 A0' |
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| ADV/LD |
| LOGIC |
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CLK | C |
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CEN |
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| WRITE ADDRESS |
| WRITE ADDRESS |
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| REGISTER 1 |
| REGISTER 2 |
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| S | O |
| O |
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| U | D |
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| E | T | U |
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| P | A | T |
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| N |
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| U | T | P |
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| ADV/LD |
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| S | T | A | U |
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| R | T |
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| WRITE REGISTRY |
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| MEMORY | E | S | B |
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| BWa |
| AND DATA COHERENCY |
| WRITE |
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| ARRAY |
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| BWb |
| CONTROL LOGIC |
| DRIVERS |
| A | G | T | U | DQPa |
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| BWc |
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| M | S | E | DQPb |
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| BWd |
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| P | T | E | E | DQPc |
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| WE |
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| S | R | R | R | DQPd |
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| S | I | S |
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| E | N | E |
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| INPUT | E |
| INPUT | E |
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| REGISTER 1 |
| REGISTER 0 |
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| OE | READ LOGIC |
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| CE1 |
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| CE2 |
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| CE3 |
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| ZZ | SLEEP |
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| CONTROL |
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Cypress Semiconductor Corporation | • | 198 Champion Court | • | San Jose, CA | • | |||||||||
Document #: |
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| Revised June 22, 2006 |
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