Cypress CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 manual Package Diagrams, Pin Tqfp 14 x 20 x 1.4 mm

Page 24

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Package Diagrams

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

1.40±0.05

100	81
1	80

22.00±0.20

20.00±0.10

0.30±0.08

0.65	12° ±1°
TYP.	(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.NOTE:

0.15 MAX.

0.10

GAUGE PLANE

0° -7°

0.60±0.15

1.00 REF.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

DETAIL A

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

51-85050-*B

Document #: 38-05353 Rev. *D

Page 24 of 27

[+] Feedback

Image 24

Contents Features Logic Block Diagram-CY7C1460AV33 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV33 2M x Logic Block Diagram-CY7C1464AV33 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionPower supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Single Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 StallFunction CY7C1460AV33 Function CY7C1462AV33 2,8TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionBall Fbga Boundary Scan Order CY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball IDBit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Ambient RangeCapacitance17 Thermal Resistance17AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25 ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History