Cypress CY7C1464AV33 manual Ball BGA Boundary Scan Order 13, CY7C14604V33 512K x Bit# Ball ID

Page 16

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

209-ball BGA Boundary Scan Order [13, 14]

CY7C14604V33 (512K x 72)

 

 

 

 

 

 

 

 

 

Bit#

Ball ID

 

Bit#

ball ID

 

Bit#

ball ID

 

Bit#

ball ID

1

W6

 

36

6F

 

71

6H

 

106

3K

 

 

 

 

 

 

 

 

 

 

 

2

V6

 

37

8K

 

72

6C

 

107

4K

 

 

 

 

 

 

 

 

 

 

 

3

U6

 

38

9K

 

73

6B

 

108

6K

 

 

 

 

 

 

 

 

 

 

 

4

W7

 

39

10K

 

74

6A

 

109

2K

 

 

 

 

 

 

 

 

 

 

 

5

V7

 

40

11J

 

75

5A

 

110

2L

 

 

 

 

 

 

 

 

 

 

 

6

U7

 

41

10J

 

76

5B

 

111

1L

 

 

 

 

 

 

 

 

 

 

 

7

T7

 

42

11H

 

77

5C

 

112

2 Mbit

 

 

 

 

 

 

 

 

 

 

 

8

V8

 

43

10H

 

78

5D

 

113

1 Mbit

 

 

 

 

 

 

 

 

 

 

 

9

U8

 

44

11G

 

79

4D

 

114

2N

 

 

 

 

 

 

 

 

 

 

 

10

T8

 

45

10G

 

80

4C

 

115

1N

 

 

 

 

 

 

 

 

 

 

 

11

V9

 

46

11F

 

81

4A

 

116

2P

 

 

 

 

 

 

 

 

 

 

 

12

U9

 

47

10F

 

82

4B

 

117

1P

 

 

 

 

 

 

 

 

 

 

 

13

P6

 

48

10E

 

83

3C

 

118

2R

 

 

 

 

 

 

 

 

 

 

 

14

W11

 

49

11E

 

84

3B

 

119

1R

 

 

 

 

 

 

 

 

 

 

 

15

W10

 

50

11D

 

85

3A

 

120

2T

 

 

 

 

 

 

 

 

 

 

 

16

V11

 

51

10D

 

86

2A

 

121

1T

 

 

 

 

 

 

 

 

 

 

 

17

V10

 

52

11C

 

87

1A

 

122

2U

 

 

 

 

 

 

 

 

 

 

 

18

U11

 

53

10C

 

88

2B

 

123

1U

 

 

 

 

 

 

 

 

 

 

 

19

U10

 

54

11B

 

89

1B

 

124

2V

 

 

 

 

 

 

 

 

 

 

 

20

T11

 

55

10B

 

90

2C

 

125

1V

 

 

 

 

 

 

 

 

 

 

 

21

T10

 

56

11A

 

91

1C

 

126

2W

 

 

 

 

 

 

 

 

 

 

 

22

R11

 

57

10A

 

92

2D

 

127

1W

 

 

 

 

 

 

 

 

 

 

 

23

R10

 

58

9C

 

93

1D

 

128

6T

 

 

 

 

 

 

 

 

 

 

 

24

P11

 

59

9B

 

94

1E

 

129

3U

 

 

 

 

 

 

 

 

 

 

 

25

P10

 

60

9A

 

95

2E

 

130

3V

 

 

 

 

 

 

 

 

 

 

 

26

N11

 

61

8D

 

96

2F

 

131

4T

 

 

 

 

 

 

 

 

 

 

 

27

N10

 

62

8C

 

97

1F

 

132

5T

 

 

 

 

 

 

 

 

 

 

 

28

M11

 

63

8B

 

98

1G

 

133

4U

 

 

 

 

 

 

 

 

 

 

 

29

M10

 

64

8A

 

99

2G

 

134

4V

 

 

 

 

 

 

 

 

 

 

 

30

L11

 

65

7D

 

100

2H

 

135

5W

 

 

 

 

 

 

 

 

 

 

 

31

L10

 

66

7C

 

101

1H

 

136

5V

 

 

 

 

 

 

 

 

 

 

 

32

K11

 

67

7B

 

102

2J

 

137

5U

 

 

 

 

 

 

 

 

 

 

 

33

M6

 

68

7A

 

103

1J

 

138

Internal

 

 

 

 

 

 

 

 

 

 

 

34

L6

 

69

6D

 

104

1K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

J6

 

70

6G

 

105

6N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

14. Bit# 138 is preset HIGH.

Document #: 38-05353 Rev. *D

Page 16 of 27

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Contents Features Logic Block Diagram-CY7C1460AV33 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV33 2M x Logic Block Diagram-CY7C1464AV33 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionPower supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Single Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Write Cycle Description 1, 2, 3 StallFunction CY7C1460AV33 Function CY7C1462AV33 2,8TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball Fbga Boundary Scan OrderBit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Ambient RangeThermal Resistance17 Capacitance17AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.