CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Functional Overview
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All writes are simplified with
Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns
Burst Read Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have an
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the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33). In addition, the address for the subse- quent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 & DQa,b/DQPa,b for CY7C1462AV33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete.
The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous
Becausethe
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) inputs. Doing so will
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) are automatically
Burst Write Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has an
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