Cypress CY7C1462AV33, CY7C1464AV33 manual NOP,STALL and Deselect Cycles24, 25, ZZ Mode Timing28

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CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Switching Waveforms (continued)

NOP,STALL and DESELECT Cycles[24, 25, 27]

CLK

CEN

ADV/LD

BWx

ADDRESS A1 A2

Data

In-Out (DQ)

WRITE	READ	STALL
D(A1)	Q(A2)

D(A1)

READ

Q(A3)

A4			A5
Q(A2)	Q(A3)		D(A4)
WRITE	STALL	NOP	READ	DESELECT
D(A4)			Q(A5)
DON’T CARE		UNDEFINED

tCHZ

Q(A5)

CONTINUE DESELECT

ZZ Mode Timing[28, 29]

CLK

ISUPPLY

ALL INPUTS (except ZZ)

Outputs (Q)

tZZ

t ZZI

I DDZZ

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

27.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

28.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

29.I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05353 Rev. *D

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Contents Logic Block Diagram-CY7C1460AV33 1M x FeaturesFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1464AV33 512K x Logic Block Diagram-CY7C1462AV33 2M xSelection Guide 250 MHz 200 MHz 167 MHz Unit2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV33 2M × Pin Name Type Pin Description Pin DefinitionsPower supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Burst Read Accesses Single Read AccessesSingle Write Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Stall Partial Write Cycle Description 1, 2, 3Function CY7C1460AV33 Function CY7C1462AV33 2,8Disabling the Jtag Feature TAP Controller Block Diagram TAP Controller State DiagramTest Access Port TAP Performing a TAP ResetTAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionBall Fbga Boundary Scan Order CY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball IDBit# Ball ID CY7C14604V33 512K x Bit# Ball ID Ball BGA Boundary Scan Order 13Maximum Ratings Electrical Characteristics Over the Operating Range15Operating Range Ambient Range Capacitance17 Thermal Resistance17 AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Read/Write/Timing24, 25 Switching WaveformsNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of Change