Cypress CY7C1462AV33 manual Clock input to the Jtag circuitry, Power supply for the I/O circuitry

Page 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1460AV33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1462AV33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1464AV33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

I/O Type

 

 

 

 

Pin Description

 

 

 

 

 

 

 

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

 

 

 

 

 

 

Clock

CEN. CLK is only recognized if CEN is active LOW.

 

 

 

1

 

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

with CE2 and CE3 to select/deselect the device.

 

 

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

 

 

 

 

 

 

Synchronous

conjunction with CE1 and CE3 to select/deselect the device.

 

 

 

3

 

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

 

 

CE

 

 

 

 

 

 

Synchronous

with CE1 and CE2 to select/deselect the device.

 

 

 

 

 

 

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device

 

 

OE

 

 

 

 

 

 

Asynchronous

to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as

 

 

 

 

 

 

 

 

 

outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is

 

 

 

 

 

 

 

 

 

masked during the data portion of a write sequence, during the first clock when emerging

 

 

 

 

 

 

 

 

 

from a deselected state and when the device has been deselected.

 

 

 

 

 

 

Input-

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by

 

 

CEN

 

 

 

 

 

 

Synchronous

the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN

 

 

 

 

 

 

 

 

 

does not deselect the device,

CEN

can be used to extend the previous cycle when required.

 

 

DQa

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

 

 

DQb

Synchronous

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

 

 

DQc

 

 

 

memory location specified by AX during the previous clock rise of the read

cycle. The

 

 

DQd

 

 

 

direction of the pins is controlled by OE and the internal control logic. When OE is asserted

 

 

DQe

 

 

 

LOW, the pins can behave as outputs. When HIGH, DQa–DQdare placed in a tri-state

 

 

DQf

 

 

 

condition. The outputs are automatically tri-stated during the data portion of a write

 

 

DQg

 

 

 

sequence, during the first clock when emerging

from a deselected state, and when the

 

 

DQh

 

 

 

device is deselected, regardless of the state of OE.

 

 

DQPa,DQPb,

I/O-

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].

 

 

DQPc,DQPd

Synchronous

During write sequences, DQPa is controlled by

BW

a, DQPb is controlled by BWb, DQPc is

 

 

DQPe,DQPf

 

 

 

controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is

 

 

DQPg,DQPh

 

 

 

controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.

 

 

MODE

Input Strap Pin

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst

 

 

 

 

 

 

 

 

 

order. Pulled LOW selects the linear burst order. MODE should not change states during

 

 

 

 

 

 

 

 

 

operation. When left floating MODE will default HIGH, to an interleaved burst order.

 

 

TDO

JTAG serial output

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

JTAG serial input

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

 

 

 

 

 

 

Synchronous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

Test Mode Select

This pin controls the Test Access Port state machine. Sampled on the rising edge of

 

 

 

 

 

 

Synchronous

TCK.

 

 

TCK

JTAG-Clock

Clock input to the JTAG circuitry.

 

 

 

 

 

 

 

VDD

Power Supply

Power supply inputs to the core of the device.

 

 

VDDQ

I/O Power Supply

Power supply for the I/O circuitry.

 

 

VSS

Ground

Ground for the device. Should be connected to ground of the system.

 

 

NC

N/A

No connects. This pin is not connected to the die.

 

 

NC/72M

N/A

Not connected to the die. Can be tied to any voltage level.

 

 

 

 

 

 

 

NC/144M

N/A

Not connected to the die. Can be tied to any voltage level.

 

 

 

 

 

 

 

NC/288M

N/A

Not connected to the die. Can be tied to any voltage level.

 

 

 

 

 

 

 

NC/576M

N/A

Not connected to the die. Can be tied to any voltage level.

 

 

 

 

 

 

 

NC/1G

N/A

Not connected to the die. Can be tied to any voltage level.

 

 

 

 

 

 

 

ZZ

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

 

 

 

 

 

 

Asynchronous

condition with data integrity preserved. During normal operation, this pin can be connected

 

 

 

 

 

 

 

 

 

to VSS or left floating. ZZ pin has an internal pull-down.

Document #: 38-05353 Rev. *D

 

 

 

 

 

 

 

 

 

Page 6 of 27

[+] Feedback

Page 5 Page 7
Image 6
Page 5 Page 7
Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV33 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionPower supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Single Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1460AV33 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1462AV33 2,8Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Scan Register SizesIdentification Codes Instruction Code DescriptionBall Fbga Boundary Scan Order CY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball IDBit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Ambient RangeCapacitance17 Thermal Resistance17AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.
Top Page Image Contents