Cypress CY7C1460AV33 Scan Register Sizes, Identification Codes, Instruction Code Description

Page 14

 

 

 

 

 

 

 

 

CY7C1460AV33

 

 

 

 

 

 

 

 

CY7C1462AV33

Scan Register Sizes

 

 

 

 

 

 

CY7C1464AV33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

Bit Size (×36)

Bit Size (×18)

 

Bit Size (×72)

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

 

 

 

3

3

 

3

 

 

 

 

 

 

 

 

 

 

 

 

Bypass

 

 

 

 

1

1

 

1

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

32

32

 

32

 

 

 

 

 

 

 

 

 

Boundary Scan Order (165-ball FBGA package)

89

89

 

-

 

 

 

 

 

 

 

 

 

Boundary Scan Order (209-ball FBGA package)

-

-

 

138

 

 

 

 

 

 

 

 

 

 

 

 

Identification Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Code

 

 

Description

 

 

 

EXTEST

 

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

 

Forces all SRAM outputs to High-Z state.

 

 

 

IDCODE

 

001

Loads the ID register with the vendor ID code and places the register between TDI and

 

 

 

 

 

TDO. This operation does not affect SRAM operations.

 

 

 

SAMPLE Z

 

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

 

Forces all SRAM output drivers to a High-Z state.

 

 

 

RESERVED

 

011

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

SAMPLE/PRELOAD

 

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

 

Does not affect SRAM operation.

 

 

 

 

RESERVED

 

101

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

 

RESERVED

 

110

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

BYPASS

 

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

 

 

 

operations.

 

 

 

 

 

Document #: 38-05353 Rev. *D

Page 14 of 27

[+] Feedback

Image 14
Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV33 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Single Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1460AV33 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1462AV33 2,8Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Scan Register SizesIdentification Codes Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan OrderCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.