Cypress CY7C1464AV33, CY7C1462AV33 manual Switching Characteristics Over the Operating Range 22

Page 19

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Switching Characteristics Over the Operating Range [22, 23]

 

 

 

 

 

 

 

 

 

 

–250

–200

–167

 

Parameter

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

tPower[18]

 

VCC (typical) to the first access read or write

1

 

1

 

1

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

4.0

 

5.0

 

6.0

 

ns

FMAX

 

Maximum Operating Frequency

 

250

 

200

 

167

MHz

tCH

 

Clock HIGH

1.5

 

2.0

 

2.4

 

ns

tCL

 

Clock LOW

1.5

 

2.0

 

2.4

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

 

Data Output Valid After CLK Rise

 

2.6

 

3.2

 

3.4

ns

tEOV

 

 

 

LOW to Output Valid

 

2.6

 

3.0

 

3.4

ns

OE

 

 

 

tDOH

 

Data Output Hold After CLK Rise

1.0

 

1.5

 

1.5

 

ns

tCHZ

 

Clock to High-Z[19, 20, 21]

 

2.6

 

3.0

 

3.4

ns

tCLZ

 

Clock to Low-Z[19, 20, 21]

1.0

 

1.3

 

1.5

 

ns

tEOHZ

 

 

 

HIGH to Output High-Z[19, 20, 21]

 

2.6

 

3.0

 

3.4

ns

OE

 

 

 

tEOLZ

 

 

 

LOW to Output Low-Z[19, 20, 21]

0

 

0

 

0

 

ns

OE

 

 

 

Set-up Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tDS

 

Data Input Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tCENS

 

 

 

 

 

 

Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

CEN

 

 

 

tWES

 

 

 

 

 

 

 

x Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

WE,

BW

 

 

 

tALS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Set-up Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tCES

 

Chip Select Set-up

1.2

 

1.4

 

1.5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

tDH

 

Data Input Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

tCENH

 

 

 

 

Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

CEN

 

 

 

tWEH

 

 

 

 

 

 

 

x Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

WE,

BW

 

 

 

tALH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV/LD

Hold after CLK Rise

0.3

 

0.4

 

0.5

 

ns

tCEH

 

Chip Select Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

Notes:

18.This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be initiated.

19.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

20.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

22.Timing reference is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V.

23.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05353 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1460AV33 1M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x Selection Guide2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV33 2M × Pin Name Type Pin Description Pin DefinitionsPower supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Burst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1462AV33 2,8 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1460AV33Performing a TAP Reset TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Test Access Port TAPTAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size ×36 Bit Size ×18 Bit Size ×72CY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball Fbga Boundary Scan OrderBit# Ball ID CY7C14604V33 512K x Bit# Ball ID Ball BGA Boundary Scan Order 13Ambient Range Electrical Characteristics Over the Operating Range15Maximum Ratings Operating RangeThermal Resistance17 Capacitance17AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Read/Write/Timing24, 25 Switching WaveformsNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of Change

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.
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