Cypress CY7C1460AV33, CY7C1462AV33 manual Interleaved Burst Address Table Mode = Floating or VDD

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CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

 

 

 

 

A1,A0

A1,A0

A1,A0

A1,A0

 

 

 

 

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

Linear Burst Address Table (MODE = GND)

First

Second

Third

Fourth

Address

Address

Address

Address

 

 

 

 

A1,A0

A1,A0

A1,A0

A1,A0

 

 

 

 

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

ZZ Mode Electrical Characteristics

Parameter

 

 

Description

 

 

 

 

 

 

 

 

Test Conditions

 

 

 

Min.

Max.

 

Unit

IDDZZ

Sleep mode standby current

 

 

ZZ > VDD − 0.2V

 

 

 

 

 

 

 

 

100

 

mA

tZZS

Device operation to ZZ

 

 

 

ZZ > VDD − 0.2V

 

 

 

 

 

 

 

 

2tCYC

 

ns

tZZREC

ZZ recovery time

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

 

 

 

 

2tCYC

 

 

ns

tZZI

ZZ active to sleep current

 

 

This parameter is sampled

 

 

 

 

 

2tCYC

 

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

 

 

 

0

 

 

 

ns

Truth Table[1, 2, 3, 4, 5, 6, 7]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

 

Used

 

 

CE

 

 

ZZ

ADV/LD

 

 

WE

 

 

 

BW

x

 

OE

 

 

CEN

 

CLK

 

DQ

 

Deselect Cycle

 

None

 

 

H

 

L

L

 

 

 

X

 

 

X

 

X

 

L

 

 

L-H

 

Tri-State

 

Continue

 

None

 

 

X

 

L

H

 

 

 

X

 

 

X

 

X

 

L

 

 

L-H

 

Tri-State

 

Deselect Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

 

External

 

 

L

 

L

L

 

 

 

H

 

 

X

 

L

 

L

 

 

L-H

 

Data Out (Q)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

 

Next

 

 

X

 

L

H

 

 

 

X

 

 

X

 

L

 

L

 

 

L-H

 

Data Out (Q)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Dummy Read

 

External

 

 

L

 

L

L

 

 

 

H

 

 

X

 

H

 

L

 

 

L-H

 

Tri-State

 

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read

 

Next

 

 

X

 

L

H

 

 

 

X

 

 

X

 

H

 

L

 

 

L-H

 

Tri-State

 

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2.Write is defined by WE and BWX. See Write Cycle Description table for details.

3.When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4.The DQ and DQP pins are controlled by the current cycle and the OE signal.

5.CEN = H inserts wait states.

6.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs=data when OE is active.

Document #: 38-05353 Rev. *D

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Contents Features Logic Block Diagram-CY7C1460AV33 1M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1462AV33 2M x Logic Block Diagram-CY7C1464AV33 512K xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Single Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Partial Write Cycle Description 1, 2, 3 StallFunction CY7C1460AV33 Function CY7C1462AV33 2,8TAP Controller Block Diagram TAP Controller State Diagram Disabling the Jtag FeatureTest Access Port TAP Performing a TAP ResetBypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan OrderCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDElectrical Characteristics Over the Operating Range15 Maximum RatingsOperating Range Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.
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