CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE = Floating or VDD)
First | Second | Third | Fourth |
Address | Address | Address | Address |
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A1,A0 | A1,A0 | A1,A0 | A1,A0 |
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00 | 01 | 10 | 11 |
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01 | 00 | 11 | 10 |
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10 | 11 | 00 | 01 |
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11 | 10 | 01 | 00 |
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Linear Burst Address Table (MODE = GND)
First | Second | Third | Fourth |
Address | Address | Address | Address |
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A1,A0 | A1,A0 | A1,A0 | A1,A0 |
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00 | 01 | 10 | 11 |
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01 | 10 | 11 | 00 |
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10 | 11 | 00 | 01 |
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11 | 00 | 01 | 10 |
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ZZ Mode Electrical Characteristics
Parameter |
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| Description |
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| Test Conditions |
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| Min. | Max. |
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IDDZZ | Sleep mode standby current |
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| ZZ > VDD − 0.2V |
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| 100 |
| mA | ||||||||||||||||
tZZS | Device operation to ZZ |
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| ZZ > VDD − 0.2V |
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| 2tCYC |
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tZZREC | ZZ recovery time |
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| ZZ < 0.2V |
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| 2tCYC |
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tZZI | ZZ active to sleep current |
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| 2tCYC |
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tRZZI | ZZ Inactive to exit sleep current | This parameter is sampled |
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| 0 |
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| ns | |||||||||||||||||||||
Truth Table[1, 2, 3, 4, 5, 6, 7] |
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| Address |
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Operation |
| Used |
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| CE |
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| ZZ | ADV/LD |
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| WE |
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| BW | x |
| OE |
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| CEN |
| CLK |
| DQ |
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Deselect Cycle |
| None |
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| H |
| L | L |
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| X |
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| X |
| X |
| L |
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Continue |
| None |
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| L | H |
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| X |
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| X |
| X |
| L |
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Deselect Cycle |
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Read Cycle |
| External |
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| L |
| L | L |
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| H |
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| X |
| L |
| L |
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| Data Out (Q) | ||||||||
(Begin Burst) |
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Read Cycle |
| Next |
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| X |
| L | H |
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| X |
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| L |
| L |
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| Data Out (Q) | ||||||||
(Continue Burst) |
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NOP/Dummy Read |
| External |
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| L |
| L | L |
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| H |
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| X |
| H |
| L |
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(Begin Burst) |
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Dummy Read |
| Next |
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| X |
| L | H |
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| X |
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| H |
| L |
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(Continue Burst) |
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Notes:
1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2.Write is defined by WE and BWX. See Write Cycle Description table for details.
3.When a write cycle is detected, all I/Os are
4.The DQ and DQP pins are controlled by the current cycle and the OE signal.
5.CEN = H inserts wait states.
6.Device will
7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX =
Document #: | Page 8 of 27 |
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