Cypress CY7C1460AV33, CY7C1464AV33 manual Logic Block Diagram-CY7C1462AV33 2M x, Selection Guide

Page 2

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Logic Block Diagram-CY7C1462AV33 (2M x 18)

 

 

 

 

 

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

REGISTER 0

A1

D1

Q1 A1'

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0 BURST Q0 A0'

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

O

 

 

 

 

 

 

 

 

 

U

 

U

 

 

 

 

 

 

 

 

S

T

D

T

 

 

 

 

 

 

 

 

P

P

 

ADV/LD

 

 

 

 

 

 

E

U

A

U

 

 

 

 

WRITE REGISTRY

 

 

 

N

T

T

T

 

 

 

 

 

 

MEMORY

S

R

A

B

 

BWa

 

 

AND DATA COHERENCY

 

WRITE

E

 

 

 

 

 

ARRAY

 

E

S

U

 

 

 

 

CONTROL LOGIC

 

DRIVERS

A

G

 

 

 

 

 

 

T

F

 

BWb

 

 

 

 

 

 

M

I

E

F

 

 

 

 

 

 

 

 

P

S

E

E

 

 

 

 

 

 

 

 

S

T

R

R

 

 

 

 

 

 

 

 

 

E

I

S

 

WE

 

 

 

 

 

 

 

R

N

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

E

 

E

 

 

 

 

 

 

 

INPUT

E

 

INPUT

E

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 0

 

OE

 

READ LOGIC

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

ZZ

 

Sleep

 

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

DQs DQPa DQPb

Logic Block Diagram-CY7C1464AV33 (512K x 72)

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

REGISTER 0

A1

D1

Q1 A1'

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0 BURST Q0 A0'

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

O

 

 

 

 

 

 

 

 

 

U

 

U

 

 

 

 

 

 

 

 

 

T

 

T

 

ADV/LD

 

 

 

 

 

 

S

P

D

P

 

 

 

 

 

 

 

E

U

A

U

 

BWa

 

 

WRITE REGISTRY

 

 

 

N

T

T

T

 

 

 

 

 

MEMORY

S

R

A

 

 

BWb

 

 

AND DATA COHERENCY

 

WRITE

E

S

B

 

 

 

CONTROL LOGIC

 

ARRAY

A

E

U

 

BWc

 

 

 

DRIVERS

 

G

T

F

 

BWd

 

 

 

 

 

 

M

I

E

F

 

 

 

 

 

 

 

P

S

E

E

 

BWe

 

 

 

 

 

 

S

T

R

R

 

 

 

 

 

 

 

E

 

BWf

 

 

 

 

 

 

 

I

S

 

 

 

 

 

 

 

 

R

N

 

 

BWg

 

 

 

 

 

 

 

S

G

 

 

 

 

 

 

 

 

 

E

E

 

BWh

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

E

 

INPUT

E

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 0

 

OE

 

READ LOGIC

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

ZZ

 

Sleep

 

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh

Selection Guide

 

250 MHz

200 MHz

167 MHz

Unit

Maximum Access Time

2.6

3.2

3.4

ns

Maximum Operating Current

475

425

375

mA

Maximum CMOS Standby

120

120

120

mA

Current

 

 

 

 

Document #: 38-05353 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1460AV33 1M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 2M ×CY7C1462AV33 2M × Pin Definitions Pin Name Type Pin DescriptionClock input to the Jtag circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Single Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1460AV33 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1462AV33 2,8Test Access Port TAP TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Performing a TAP ResetBypass Register TAP Instruction SetOutput Times TAP TimingParameter Description Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size ×36 Bit Size ×18 Bit Size ×72 Scan Register SizesIdentification Codes Instruction Code DescriptionBit# Ball ID Ball Fbga Boundary Scan OrderCY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball ID Ball BGA Boundary Scan Order 13 CY7C14604V33 512K x Bit# Ball IDOperating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance17Thermal Resistance17 Switching Characteristics Over the Operating Range 22 250 200 167 Parameter Description Unit Min MaxSwitching Waveforms Read/Write/Timing24, 25ZZ Mode Timing28 NOP,STALL and Deselect Cycles24, 25Ordering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History

CY7C1462AV33, CY7C1464AV33, CY7C1460AV33 specifications

The Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 are high-performance, low-power asynchronous SRAM devices that find wide applications in various electronic systems, encompassing telecommunications, computing, and consumer electronics. These SRAM products are particularly popular for their speed, efficiency, and versatility in a range of data processing applications.

A key feature of the CY7C1460AV33 is its 64K x 16 memory architecture, while the CY7C1464AV33 offers a 256K x 16 configuration, and the CY7C1462AV33 provides a 128K x 16 setup. This allows designers to tailor their memory requirements based on the specific demands of their applications, promoting system optimization and enhancing performance.

One of the standout characteristics of these SRAM devices is their high-speed operation. With access times as low as 10 nanoseconds, they are capable of supporting demanding applications that necessitate rapid data retrieval and storage. This performance is complemented by a low cycle time, which contributes to faster data rates, enabling seamless data flow and efficient processing capabilities.

Low power consumption is another defining feature of the CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33. These devices utilize advanced CMOS technology, ensuring minimal energy usage without sacrificing performance. This is particularly advantageous for battery-operated devices and applications where energy efficiency is critical.

The SRAM devices also boast robust reliability and environmental tolerance. They are designed to operate over a wide temperature range, making them suitable for various operating conditions. Additionally, the use of advanced process technology ensures data integrity and durability, allowing them to survive in harsh environments.

Furthermore, the devices support a simple interfacing design, enabling easy integration into existing systems. They feature dual-chip select and byte write functionality, which enhances flexibility in memory handling, providing the capability to manage data more effectively.

In summary, the Cypress CY7C1460AV33, CY7C1464AV33, and CY7C1462AV33 offer high-speed, low-power, and highly reliable SRAM solutions suitable for various applications. With their advanced technology and robust characteristics, these devices are invaluable in modern electronic design, enabling innovation and performance optimization across diverse fields.