Cypress CY7C1462AV33 manual Document History, ECN No Issue Date Orig. Description of Change

Page 27

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Document History Page

Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05353

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

254911

See ECN

SYT

New Data sheet

 

 

 

 

Part number changed from previous revision. New and old part number differ

 

 

 

 

by the letter “A”

*A

303533

See ECN

SYT

Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209

 

 

 

 

FBGA on Page # 5

 

 

 

 

Changed the test condition from VDD = Min to VDD = Max for VOL in the

 

 

 

 

Electrical Characteristics table

 

 

 

 

Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All

 

 

 

 

Packages on the Thermal Resistance Table

 

 

 

 

Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200

 

 

 

 

and 167 MHz respectively

 

 

 

 

Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167

 

 

 

 

MHz respectively

 

 

 

 

Changed ISB2 from 80 mA to 100 mA for all frequencies

 

 

 

 

Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 MHz

 

 

 

 

respectively

 

 

 

 

Changed ISB4 from 100 mA to 110 mA for all frequencies

 

 

 

 

Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP

 

 

 

 

Package

 

 

 

 

Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 MHz

 

 

 

 

Speed Bin

 

 

 

 

Added lead-free information for 100-pin TQFP and 165 FBGA and 209 BGA

 

 

 

 

packages

*B

331778

See ECN

SYT

Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA

 

 

 

 

Package as per JEDEC standards and updated the Pin Definitions accord-

 

 

 

 

ingly

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA

 

 

 

 

Package

 

 

 

 

Added Industrial Temperature Grade

 

 

 

 

Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively

 

 

 

 

Updated the Ordering Information by Shading and Unshading MPNs as per

 

 

 

 

availability

*C

417509

See ECN

RXU

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed IX current value in MODE from –5 & 30 ∝A to –30 & 5 ∝A respec-

 

 

 

 

tively and also Changed IX current value in ZZ from –30 & 5 ∝A to –5 & 30

 

 

 

 

∝A respectively on page# 18

 

 

 

 

Modified test condition from VIH < VDD to VIH < VDD

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

 

 

 

 

Electrical Characteristics Table

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Replaced Package Diagram of 51-85050 from *A to *B

*D

473229

See ECN

NXR

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05353 Rev. *D

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1460AV33 1M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1462AV33 2M xLogic Block Diagram-CY7C1464AV33 512K x Selection Guide2M × Pin Configurations Pin Tqfp PinoutCY7C1462AV33 2M × Pin Name Type Pin Description Pin DefinitionsPower supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Burst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1462AV33 2,8 Partial Write Cycle Description 1, 2, 3Stall Function CY7C1460AV33Performing a TAP Reset TAP Controller Block Diagram TAP Controller State DiagramDisabling the Jtag Feature Test Access Port TAPTAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size ×36 Bit Size ×18 Bit Size ×72Ball Fbga Boundary Scan Order CY7C1460AV33 1M x 36, CY7C1462AV33 2M x Bit# Ball IDBit# Ball ID CY7C14604V33 512K x Bit# Ball ID Ball BGA Boundary Scan Order 13Ambient Range Electrical Characteristics Over the Operating Range15Maximum Ratings Operating RangeCapacitance17 Thermal Resistance17AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 22Read/Write/Timing24, 25 Switching WaveformsNOP,STALL and Deselect Cycles24, 25 ZZ Mode Timing28Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of Change
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