Texas Instruments TMS320C6201 manual DMA Paused During Emulation Halt

Page 10

TMS320C6201 Silicon Errata

SPRZ153

Advisory 3.1.6

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.7

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.8

Revision(s) Affected:

Details:

Workaround:

DMA Paused During Emulation Halt

3.1, 3.0, 2.1, and 2.0

When running an autoinitialized transfer, the DMA write state machine is halted during an emulation halt regardless of the value of EMOD in the DMA Channel Primary Control Register. The read state machine functions properly in this case. The problem exists only at block boundaries. If EMOD = 1, this problem is irrelevant since the DMA channel is expected to pause during an emulation halt. (Internal reference number C601301)

There is no workaround for EMOD = 0. Expect DMA transfers to pause when the emulator stops the processor.

DMA: RSYNC = 10000b (DSPINT) Does Not Wait for Sync

3.1, 3.0, 2.1, and 2.0

If RSYNC in the DMA Channel Primary Control Register is set to host-port host-to-DSP interrupt (DSPINT – 10000b), the DMA channel would do the read transfer without waiting for the sync event. There is not a problem if WSYNC is set to DSPINT. (Internal reference number C601302)

Do not use synchronized DMA reads to DSPINT. If a DMA read is desired during a host-port host-to-DSP interrupt, set RSYNC in the Primary Control Register to one of the EXT_INT events instead (EXT_INT4 – EXT_INT7) and have the host trigger an interrupt on that pin rather than by writing to HPIC.

EMIF: Invalid SDRAM Access to Last 1K Byte of CE3

3.1, 3.0, 2.1, and 2.0

If 16M bytes of SDRAM (two 64M bits in a 1M X 16x4 organization) is used in CE3, you can have invalid accesses to the last 1K byte of CE3 (0x03FFFC00).

This occurs when the following is true:

•After a DCAB (deactivate all pages) to all SDRAM CE spaces (forced by Refresh or MRS command)

•The first access to CE3 is to the last page of CE3 (0x03FFFC00).

•Then a page activate will not be issued to CE3. Since the SDRAM in CE3 is in a deactivated state at that point, invalid accesses will occur. (Internal reference number C630280)

Best Case: Avoid designing a board with a 64M-bit (1M X 16x4) SDRAM mapped into CE3.

10

Page 9 Page 11
Image 10
Page 9 Page 11
Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Issues When Pausing at a Block Boundary AdvisoryDMA Stopped Transfer Reprogrammed Does Not Wait for Sync DMA Freezes if Postincrement/Decrement Across Port BoundaryDMA Paused During Emulation Halt Emif Invalid Sdram Access to Last 1K Byte of CE3DMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHz Write Example Desired BehaviorRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif Sdram Invalid Access Emif CE Space Crossing on Continuous Request Not AllowedDMA Rsync Cleared Late for Frame-synchronized Transfer McBSP DXR to XSR Copy Not GeneratedFor big-endian mode DMA Split-mode End-of-frame Indexing DMA Channel 0 Multiframe Split-Mode Incompletion Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode Emif RBTR8 Bit Not FunctionalMcBSP Incorrect mLaw Companding Value Emif Hold Feature Improvement on RevisionFalse Cache Hit Extremely Rare Emif Hold Request Causes Problems With Sdram Refresh DMA Priority Ignored by PbusDMA Split-mode Receive Transfer Incomplete After Pause Bootload HPI Feature Improvement on RevisionDMA Multiframe Transfer Data Lost During Stop Pmemc Branch from External to Internal DMA DMA Data Block Corrupted After Start Zero Transfer CountProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP New Block Interrupt Does Not Occur for Start of Block McBSP Frst Improved in 2.1 overEmif Multiple Sdram CE Spaces Invalid Access After Refresh McBSP Xempty Stays Low When DXR Written LateDMA/Internal Data Memory Conflict Data Corruption Emif Data Setup Times Documentation SupportImportant Notice
Top Page Image Contents