Texas Instruments TMS320C6201 manual McBSP Xempty Stays Low When DXR Written Late

Page 27

TMS320C6201 Silicon Errata

SPRZ153

Advisory 2.0.13

Revision(s) Affected:

Details:

Advisory 2.0.14

Revision(s) Affected:

Details:

Workaround:

Advisory 2.0.18

Revision(s) Affected:

Details:

Workaround:

McBSP: XEMPTY Stays Low When DXR Written Late

2.0

XEMPTY goes low and stays low when DXR was written on either the last bit or next-to-last bit of the previous word being transferred to DX. (Internal Reference Number 3383)

EMIF: Multiple SDRAM CE Spaces: Invalid Access After Refresh

2.0

This bug exists only in those systems that have SDRAMs in more than one CE space. When there are two SDRAM accesses performed to two CE spaces, followed by a refresh, the pages in all CE spaces with SDRAM are deactivated. The first CE space to be accessed after the refresh is activated correctly. The bug is that if the second CE space is accessed on the same page as before the refresh, it will not be activated before the read or write is attempted. (Internal Reference Number 3952)

Avoid use of multiple CE spaces of SDRAM within a single refresh period.

DMA/Internal Data Memory: Conflict Data Corruption

2.0

This bug occurs when the CPU has high priority and is accessing a bank with word access (load or store) followed by similar (load or store) half-word access, and the DMA is also accessing the same bank simultaneously with word accesses:

Example:

LDW

.D1

*A3, A4

 

 

LDW

.D2

*A3, A5

; A DMA to the bank containing never completes

 

 

 

; but the DMA continues as if it did

The data transfer done by the DMA is corrupted in half-words (or rather not updated) when the DMA transfer is complete. (Internal Reference Number 4195)

When DMAing to/from internal memory with DMA in low priority, use half-word or byte element size transfers. Alternatively, avoid the above code sequence during DMA transfers.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncEmif Invalid Sdram Access to Last 1K Byte of CE3 DMA Paused During Emulation HaltDMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Emif RBTR8 Bit Not Functional Timer Clock Output Not Driven for External ClockPower-Down Pin PD Not Set High for Power-Down 2 Mode DMA Channel 0 Multiframe Split-Mode IncompletionEmif Hold Feature Improvement on Revision McBSP Incorrect mLaw Companding ValueFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshBootload HPI Feature Improvement on Revision DMA Split-mode Receive Transfer Incomplete After PauseDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockMcBSP Xempty Stays Low When DXR Written Late Emif Multiple Sdram CE Spaces Invalid Access After RefreshDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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