Texas Instruments TMS320C6201 manual DMA Stopped Transfer Reprogrammed Does Not Wait for Sync

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TMS320C6201 Silicon Errata

SPRZ153

Advisory 3.1.3

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.4

Revision(s) Affected:

Details:

Workaround:

Advisory 3.1.5

Revision(s) Affected:

Details:

Workaround:

DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional

3.1, 3.0, 2.1, and 2.0

If a DMA channel is configured to do a multiframe split-mode transfer with SRC_DIR = Index (11b), the source address is always modified using the Element Index, even during the last element transfer of a frame. The transfer of the last element in a frame should index the source address using the Frame Index instead of the Element Index. DST_DIR = 11b functions properly. (Internal reference number C601256)

For multiframe transfers, use two DMA channels instead of using the split mode. Source Index works properly for non-split-mode transfers.

DMA: Stopped Transfer Reprogrammed Does Not Wait for Sync

3.1, 3.0, 2.1, and 2.0

If any non-synchronized transfer (e.g., auto-init transfer) is stopped, and then the same channel is programmed to do a write-synchronized transfer (e.g., split-mode transfer), the write transfer does not wait for the sync event. (Internal reference number C601261)

Perform a nonsynchronized dummy transfer of one element to/from the same location before starting the synchronized transfer.

DMA Freezes if Postincrement/Decrement Across Port Boundary

3.1, 3.0, 2.1, and 2.0

For any DMA transfers with source/destination address postincrement/decrement, if the last element to be transferred is aligned on a port boundary, then the DMA may freeze before transferring this element. A port boundary is the address boundary between external memory and program memory, between external memory and the peripheral address space, or between program memory and the peripheral address space.

The following conditions cause DMA to freeze:

•For non-sync and frame-sync transfers: if a channel is paused after the second-to-last element is read, the DMA will freeze when the channel is then restarted with a request to the address at a port boundary.

•For split-mode transfers or read/write-sync transfers: the DMA will freeze while transferring the element aligned on the port boundary. A continuous burst transfer with post-increment/decrement source/destination address does not exhibit this problem. (Internal reference number C601300)

Do not transfer to boundary addresses if the DMA source/destination address is post-incremented/

decremented.

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Contents TMS320C6201 Digital Signal Processor Silicon Errata Contents TMS320C6201 Silicon Errata Introduction Dspdsp Sbsram Read Timing 1/2 Rate Ssclk See Note Sbsram Write Timing 1/2 Rate Ssclk See Note Advisory Issues When Pausing at a Block BoundaryDMA Freezes if Postincrement/Decrement Across Port Boundary DMA Stopped Transfer Reprogrammed Does Not Wait for SyncEmif Invalid Sdram Access to Last 1K Byte of CE3 DMA Paused During Emulation HaltDMA Rsync = 10000b Dspint Does Not Wait for Sync Cache During Emulation With Extremely Slow External Memory Write Example Desired Behavior Emif Inverted Sdclk and Ssclk at Speeds Above 175 MHzRead Example Desired Behavior CPU L2-unit Long Instructions Corrupted During Interrupt Emif CE Space Crossing on Continuous Request Not Allowed Emif Sdram Invalid AccessMcBSP DXR to XSR Copy Not Generated DMA Rsync Cleared Late for Frame-synchronized TransferFor big-endian mode DMA Split-mode End-of-frame Indexing Power-Down Pin PD Not Set High for Power-Down 2 Mode Timer Clock Output Not Driven for External ClockDMA Channel 0 Multiframe Split-Mode Incompletion Emif RBTR8 Bit Not FunctionalEmif Hold Feature Improvement on Revision McBSP Incorrect mLaw Companding ValueFalse Cache Hit Extremely Rare DMA Priority Ignored by Pbus Emif Hold Request Causes Problems With Sdram RefreshBootload HPI Feature Improvement on Revision DMA Split-mode Receive Transfer Incomplete After PauseDMA Multiframe Transfer Data Lost During Stop DMA DMA Data Block Corrupted After Start Zero Transfer Count Pmemc Branch from External to InternalProgram Fetch Cache Modes Not Functional Emif Reserved Fields Have Incorrect Values McBSP Frst Improved in 2.1 over McBSP New Block Interrupt Does Not Occur for Start of BlockMcBSP Xempty Stays Low When DXR Written Late Emif Multiple Sdram CE Spaces Invalid Access After RefreshDMA/Internal Data Memory Conflict Data Corruption Documentation Support Emif Data Setup TimesImportant Notice
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